Static semiconductor memory device

Details Static semiconductor memory device Static semiconductor memory device

2002-12-30

2004-06-08

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000

Reexamination Certificate

active

06747323

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to static semiconductor memory devices (hereinafter abbreviated as “SRAMs”) and, more particularly, to an SRAM capable of preventing soft errors.
2. Description of the Background Art
In recent years, semiconductor devices of portable apparatuses are required to operate at less energy and low voltage to provide longer battery life. Accordingly, the demand for SRAMs designed for low voltage operation with less power consumption has been on the increase. Such SRAMs for low voltage operation generally have six transistors and usually employ what is called a full CMOS (Complementary Metal-Oxide Semiconductor) memory cell.
FIG. 39
shows an equivalent circuit of a conventional SRAM memory cell. Referring to
FIG. 39
, a memory cell
100
z
of the SRAM includes n channel drive transistors
101
and
104
, p channel load transistors
102
and
105
, and n channel access transistors
103
and
106
.
Memory cell
100
z
is connected to bit lines
171
and
172
, a word line
199
, a power supply node
175
, and ground nodes
173
and
174
. In memory cell
100
z
of the SRAM, drive transistors
101
and
104
as well as load transistors
102
and
105
form a flip flop circuit.
Load transistor
102
has its source region connected to power supply node
175
and drain region connected to a storage node
116
. A gate electrode
111
of load transistor
105
is connected to a storage node
115
.
Load transistor
105
has its source region connected to power supply node
175
and drain region connected to storage node
115
. A gate electrode
112
of load transistor
105
is connected to storage nodes
116
.
Drive transistor
101
has its source region connected to a ground node
173
and drain region connected to storage node
116
. Gate electrode
111
of drive transistor
101
is connected to storage node
115
.
Drive transistor
104
has its source region connected to a ground node
174
and drain region connected to storage node
115
. Gate electrode
112
of drive transistor
104
is connected to storage node
116
.
A gate electrode
113
of access transistor
103
is connected to word line
199
. One of source and drain regions of access transistor
103
is connected to bit line
171
, and the other connected to storage node
116
.
Gate electrode
113
of access transistor
106
is connected to word line
199
. One of source and drain regions of access transistor
106
is connected to bit line
172
, and the other connected to storage node
115
.
As shown in
FIG. 39
, memory cell
100
z
of the SRAM has an inverter formed by drive transistor
101
of an n channel transistor and a load transistor
102
of a p channel transistor. Further, it has an inverter formed by drive transistor
104
of an n channel transistor and load transistor
105
of a p channel transistor. These two inverters are combined and connected. An output of each inverter is an output of the other inverter, creating a stabilized state. These outputs are further connected to bit lines
171
and
172
through access transistors
103
and
106
. When access transistors
103
and
106
are turned on, data are written to or read from bit lines
171
and
172
.
In memory cell
100
z
shown in
FIG. 39
, when a potential at storage node
116
is relatively high, a potential at storage node
115
is relatively low. On the contrary, when the potential at storage node
116
is relatively low, the potential at storage node
115
is relatively high. These two states are used for storage of the presence of data.
FIG. 40
shows a plan view of the memory cell of the conventional SRAM shown in FIG.
39
. Referring to
FIG. 40
, memory cell
100
z
of the SRAM includes a pair of load transistors
102
and
105
, a pair of drive transistors
101
and
104
, and a pair of access transistors
103
and
106
.
Access transistor
103
has a pair of n-type impurity regions formed in an active region
130
, and gate electrode
113
. One of the impurity regions is connected to bit line
171
through contact hole
303
, and the other connected to storage node
116
through a contact hole
302
.
Access transistor
106
has a pair of n-type impurity regions formed in an active region
150
, and gate electrode
113
. One of the impurity regions is connected to bit line
172
through a contact hole
309
, and the other connected to storage node
115
through a contact hole
206
.
Drive transistor
101
has a pair of n-type impurity regions formed in active region
130
, and gate electrode
111
. One of the impurity regions is connected to ground node
173
through a contact hole
307
, and the other connected to storage node
116
through contact hole
302
.
Drive transistor
104
has a pair of n-type impurity regions formed in an active region
150
, and gate electrode
112
. One of the impurity regions is connected to ground node
174
through a contact hole
308
, and the other connected to storage node
115
through contact hole
206
.
Load transistor
102
has a pair of p-type impurity regions formed in an active region
140
, and gate electrode
111
. One of the impurity regions is connected to storage node
116
through a contact hole
301
, and the other connected to power supply node
173
through a contact hole
305
.
Load transistor
105
has a pair of p-type impurity regions formed in an active region
160
, and gate electrode
112
. One of the impurity regions is connected to storage node
115
through a contact hole
205
, and the other connected to power supply node
175
through a contact hole
306
.
FIG. 41
is a cross sectional view taken along the line XLI—XLI in FIG.
40
. Referring to
FIG. 40
, an isolation oxide film
2
is formed above a silicon substrate
1
. A p-type well region
107
p
and an n-type well region
108
n
are formed on the surface of silicon substrate
1
. Active region
130
is formed in p-type well region
107
p
. Formed in p-type well region
107
p
are a pair of low-concentration impurity regions
131
a
and
131
b
as well as a pair of high-concentration impurity regions
132
a
and
132
b
, with each pair of regions being spaced apart from each other. Low-concentration impurity regions
131
a
,
131
b
and high-concentration impurity regions
132
a
,
132
b
form what is called an LDD (Lightly Doped Drain) structure. A channel dope region
133
p
of a p-type impurity region is formed between the pair of low-concentration impurity regions
131
a
and
131
b.
Gate electrode
113
is formed on silicon substrate
1
with a gate insulative film
113
a
interposed. A side surface of gate electrode
113
is covered with a sidewall oxide film
121
and an upper surface thereof is covered with an upper oxide film
122
. Gate electrode
111
is formed on isolation oxide film
2
. Gate electrode
111
is also covered with sidewall oxide film
121
and upper oxide film
122
.
Active region
140
is formed in n-type well region
108
n
. Active region
140
has p type low-concentration impurity region
141
a
and p type high-concentration impurity region
142
a.
An interlayer insulative film
200
is formed to cover silicon substrate
1
. Formed in interlayer insulative film
200
are contact holes
204
,
203
,
202
, and
201
, respectively reaching low-concentration impurity regions
131
a
,
131
b
, gate electrode
111
, and low-concentration impurity region
141
a
. Plug layers
221
to
224
are respectively formed in contact holes
201
to
204
. Pad electrodes
211
,
212
, and
213
are formed on interlayer insulative film
200
respectively to have contact with plug layers
221
,
223
, and
224
. Storage node
115
is formed on interlayer insulative film
200
to have contact with plug layer
222
.
An interlayer insulative film
300
is formed to cover interlayer insulative film
200
. Formed in interlayer insulative film
303
are contact holes
301
,
302
, and
303
, respectively reaching pad electrodes
211
,
212
, and
213
. Plug layers
321
to
323
are respectively formed in contact holes
301
to
303
. Sto

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