Static semiconductor memory device

Details Static semiconductor memory device Static semiconductor memory device

2003-02-11

2004-03-23

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000, C257S382000, C257S903000

Reexamination Certificate

active

06710412

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor memory device (hereinafter, referred to as “SRAM (Static Random Access Memory)”), and more particularly to a memory cell structure of a CMOSSRAM.
2. Description of the Background Art
FIG. 14
shows the conventional layout configuration of a non-load SRAM memory cell formed from four tansistors.
FIG. 12
is an equivalent circuit diagram of FIG.
14
.
The SRAMs of this type are described in, for example, “A 1.9-&mgr;m
2
Loadless CMOS Four-Transistor SRAM Cell In a 0.18-&mgr;m Logic Tecnology”, international journal IEDM '98, pp. 643-646 and “An Ultrahigh-Density High-Speed Load less Four-Tristor SRAM Macro with Twisted Bit Line Architecture and Triple-Well Shield”, international journal IEEE JSSC VOL. 36, No. 3, March 2001.
As shown in
FIG. 14
, a memory cell
1
includes four MOS (Metal Oxide Semiconductor) transistors. Specifically, memory cell
1
includes NMOS transistors N
1
and N
2
in a P well and PMOS transistors P
1
and P
2
in an N well.
NMOS transistor N
1
is located at an intersection between an N-type diffusion region
2
a
and a polysilicon wiring
3
c
, and NMOS transistor N
2
is located at an intersection between an N-type diffusion region
2
b
and a polysilicon wiring
3
b
. PMOS transistor P
1
is located at an intersection between a P-type diffusion region
2
c
and a polysilicon wiring
3
a
, and PMOS transistor P
2
is located at an intersection between a P-type diffusion region
2
d
and a polysilicon wiring
3
a.
PMOS transistors P
1
and P
2
are access transistors and NMOS transistors N
1
and N
2
are driver transistors. Diffusion regions
2
a
to
2
d
are connected to upper layer wirings through contact holes
4
a
to
4
h
, respectively.
With the layout configuration shown in
FIG. 14
, a word line WL is arranged in a lateral direction while bit line pairs BL
1
and BL
2
are arranged in a longitudinal direction. As shown in
FIG. 14
, the layout configuration of one bit is long in the longitudinal direction and a bit line, therefore, becomes long in this configuration. In addition, high resistance polysilicon wirings
3
b
and
3
c
are present on the path (path for pulling out bit lines) between a bit line and a GND line.
As described above, since the conventional four-transistor SRAM memory cell is long in a bit line direction, the wiring capacitance of each bit line is high. Due to this, access time is slow. Further, since high resistance polysilicon wirings
3
b
and
3
c
are present on the paths between bit line contact sections (contact holes
4
f
and
4
h
) and ground contact sections (contact holes
4
a
and
4
c
), respectively, the resistance of each path is high. The high resistance of the path also causes a delay in access time, disadvantageously hampering increasing the see of the SRAM.
Furthermore, the direction of the gates and diffusion regions of access transistor and P
2
differ from that of the gates and diffusion regions of driver transistors N
1
and N
2
. Due to this, variations in the widths and positions of formation patterns for gates or the like become large after photolithographic processing. If variations in gate width and the like become large, the characteristics of the respective tranistors disadvantageously change.
Moreover, if the position at which polysilicon wiring
3
c
is formed is deviated horizontally, for example, in
FIG. 14
, a short circuit is generated between polysiicon wiring
3
c
and contact hole
4
a
or
4
b
. If the position at which polysilicon wiring
3
a
is formed is deviated vertically, for example, in
FIG. 14
, a shortcuit is generated between polysilicon wiring
3
a
and contact holes
4
e
to
4
h
. As can be seen, even if a gate pattern is deviated either vertically or horizontally, a short-circuit may possibly be generated between the polysilicon wiring and the contact hole which should be separated from each other, making it disadvantageously difficult to secure a margin for manufacturing irregularities caused by a mask error or the like.
SUMMARY OF THE INVENTION
The present invention has been achieved to solve the above described disadvantages. It is an object of the present invention to accelerate an SRAM and to secure a manufacturing irregularity margin.
According to one aspect of the present invention, a static semiconductor memory device includes: first and second bit lines; a word line; first and second access MOS transistors of a first conductive type, having sources connected to the first and second bit lines, respectively, and having gates connected to the word line in common; and first and second driver MOS transistors of a second conductive type different from the first conductive type, having sources applied with a ground potential, having drains connected to drains of the first and second access MOS transistors, respectively, and having gates connected to the drains of the second and first access MOS transistors, respectively. The drain of the first access MOS transistor is connected to the drain of the first driver MOS transistor by using a metal wiring without interposing a gate of the second driver MOS transistor therebetween, and the drain of the second access MOS transistor is connected to the drain of the second driver MOS transistor by using a metal wiring without interposing a gate of the first driver MOS transistor therebetween.
As can be seen, an access MOS transistor is connected to each driver MOS transistor by using a metal wiring lower in r than an ordinary gate without interposing the gate of the other driver MOS transistor therebetween. It is, therefore, possible to decrease the resistance between the bit line and the ground line. It is thereby possible to accelerate an SRAM.
According to another aspect of the present invention, a static semiconductor memory device includes: first and second access MOS tranistors of a second conductive type, formed on a first well of a first conductive type; first and second driver MOS transistors of the first conductive type, formed on a second well of the second conductive type; a word line connected to gates of the first and second access MOS transistors, and extending in a direction in which the first and second wells are aligned; and first and second bit lines connected to sources of the first and second access MOS transistors, respectively, and extending in a direction perpendicular to the direction in which the first and second wells are aligned First and second diffusion regions of the second conductive type for forming sources and drains of the first and second access MOS transistors are extended in a same direction as a direction in which third and fourth diffusion regions of the first conductive type for forming sources and drains of the first and second driver MOS transistors are extended, gates of the first and second access MOS transistors are extended in a same direction as a direction in which gates of the first and second driver MOS transistors are extended, and the drains of the first and second access MOS transistors are connected to the drains of the first and second driver MOS transistors by using first and second metal wirings without interposing the gates of the first and second driver MOS tranistors therebetween, respectively.
As described above, by connecting the drain of an access MOS transistor to the drain of a driver MOS transistor by using a metal wiring without interposing the gate of the driver MOS tansistors therebetween, it is possible to avoid interposing a polysilicon wiring on the path between these drains. It is thereby possible to decrease the resistance of the path. In addition, since the bit lines are extended in the direction perpendicular to the direction in which the first and second wells are aligned, it is possible to reduce the length of each bit line. Further, since the first, second, third and fourth diffusion regions (active regions) are extended in the same direction and the gate of an access MOS transactor is extended in the same direction in which t

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