Static random access memory with PMOS pass gates

Details Static random access memory with PMOS pass gates Static random access memory with PMOS pass gates

1990-04-06

1992-06-30

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365190, 36523003, G11C 700

Patent

active

051269708

ABSTRACT:
An SRAM uses PMOS column pass gates in conjunction with PMOS column loads which can be selectively deactivated during write operations. Address decoding for the pass gates and loads can be done outside of the memory array to maximize device density. This arrangement provides densities comparable to those achievable with NMOS column pass gates, but without the read access time penalties associated therewith.

REFERENCES:
patent: 4648074 (1987-03-01), Pollachek
patent: 4665507 (1987-05-01), Gondou et al.
patent: 4935898 (1990-06-01), Miyaoka et al.
Fumio Miyaji et al., "A 25ns 4Mb CMOS SRAM with Dynamic Bit Line Loads", IEEE International Solid-State Circuits Conference, Session 16. Feb. 17, 1989, pp. 250-251.
Hiroaki Okuyama et al., "A 7.5ns 32K.times.8 CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1054-1056.
Hiroshi Shimada et al., "A 18-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, p. 1073.
Yoshio Kohno et al., "A 14-ns-Mbit CMOS SRAM with Varible Bit Organization", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1060-1061.
Katsuro Sasaki et al., "A 15-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, p. 1067.
Wong et al., "A 11-ns 8K.times.18 CMOS State RAM with 0.5-.mu.m Devices", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, p. 1101.

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