Static random access memory (SRAM) without precharge circuitry

Details Static random access memory (SRAM) without precharge circuitry Static random access memory (SRAM) without precharge circuitry

2003-04-03

2004-11-09

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S230060

Reexamination Certificate

active

06816401

ABSTRACT:

BACKGROUND
1. Field of Invention
The present invention relates to semiconductor memories, and in particular, to static random access memories (SRAMs).
2. Related Art
In general, a static random access memory (SRAM) cell includes a bistable flipflop, where the flipflop is formed from two cross-coupled transistors that store the data and two load elements. The cross-coupled or storage transistors are typically NMOS transistors, while the load elements may be enhancement or depletion mode transistors, PMOS transistors, or load resistors in different configurations. An access or select transistor is coupled between each storage transistor and load element to access the corresponding storage transistor for reading (accessing the data stored) from or writing (storing data) to the transistor. The load elements offset any charge leakage at the drains of the storage transistors that may corrupt the data. Since the memory cell is static, e.g., the cell has an internal feedback to maintain a stable output voltage, the data remains stored in latches without having to periodically refresh the memory as long as power is maintained to the memory cell.
An array of such SRAM cells may be configured in rows and columns to form a memory array, e.g. a 16K RAM.
FIG. 1
shows a portion of a typical SRAM memory array with an SRAM cell
100
. SRAM cell
100
includes two NMOS transistors
102
and
104
and two PMOS transistors
106
and
108
, each NMOS/PMOS pair coupled together to form an inverter. The gates of NMOS transistor
102
and PMOS transistor
106
are connected to each other as are the drains. NMOS transistor
104
and PMOS transistor
108
are similarly connected. Further, the commonly connected drains of transistors
102
and
106
(or the output of the inverter) are coupled to the gates of transistors
104
and
108
, while the commonly connected drains of transistors
104
and
108
are coupled to the gates of transistors
102
and
106
, i.e., cross-coupled. The sources of NMOS transistors
102
and
104
are coupled to a first reference voltage Vss or ground, and the sources of PMOS transistors
106
and
108
are coupled. to a second reference voltage Vdd or supply voltage.
An access or select transistor
110
is coupled between the drains of transistors
102
and
106
and a bit line
114
. A second access or select transistor
112
is coupled between the drains of transistors
104
and
108
and a second bit line or {overscore (bit)} line
116
, which is the complement of bit line
114
. In an SRAM array, there are multiple word lines and bit line pairs (the true and complement) arranged in the row and column directions, respectively. Thus, each SRAM cell has a corresponding word line and two bit lines (bit and {overscore (bit)}). In some configurations, the bit lines may be connected to data lines for writing to or reading from the SRAM cells. As is known in the art, address decoder circuits (e.g., row and column decoders) select the SRAM cell to be written to or read from by turning on the appropriate select or access transistor, and control signals determine whether the operation will be a read or write for the selected memory cell. Depending on the configuration, an SRAM cell may have two, four (two for each port), or more access transistors.
Typically, for maximum circuit density, the size of the inverters formed from transistors
102
/
106
and
104
/
108
are minimized and are thus unable to provide sufficient power to bring the respective bit line
114
and {overscore (bit)} line
116
to a true logic-zero or logic-one state as quickly as desired. That is, they are insufficiently sized to sink or source the charge on the lines so that one of the lines is brought quickly to a ground potential Vss, and one of the lines is brought quickly to the power supply potential Vdd, respectively. Thus, a differential detector or sense amplifier (not shown) is typically provided to sense a difference between the voltages on bit line
114
and {overscore (bit)} line
116
, and produces the appropriate logic output value corresponding to the state of the memory cell.
To properly and quickly detect the voltage differential at bit line
114
and {overscore (bit)} line
116
, bit line
114
and {overscore (bit)} line
116
are “precharged” to a known voltage before the selected memory cell is connected to the bit lines. The known voltage is typically selected to be a voltage that is neither sufficiently high nor sufficiently low to cause either of the two inverters (transistors
102
/
106
or transistors
104
/
108
) in the memory cell to change state. Precharge circuits are well known, some typically precharging the bit lines to a voltage level that is approximately equal to half the supply voltage Vdd, i.e., vdd/2. Precharge circuits are coupled to the bit lines and have control signals that determine when the bit lines are to be charged.
In typical operation, the voltage output of the precharge circuit is placed on both bit line
114
and {overscore (bit)} line
116
and charges the lines to the nominal voltage level of Vdd/
2
before a read operation, in one example. In some precharge circuits, a pass transistor couples the supply voltage to the bit lines. Once the pass transistor is turned on, the connected bit line will charge to a level lower than the supply voltage because the pass transistor only remains on when the potential difference between the gate and source (or drain) of the pass transistor is at least as great as the threshold voltage. Thus, the bit line charges to a level that is a threshold voltage below the supply voltage. Typically, both bit lines are precharged to the same level, e.g., by connecting the two by another pass transistor.
Having precharged each bit line to the same voltage level, the particular memory cell can be selected for a “read” of the value contained within the memory cell. Because the SRAM cell contains opposing inverters, the voltage level on one of the bit lines
114
or
116
increases, while the voltage at the other of the bit lines decreases, depending upon the logic value stored in the cell, as determined by the state of the cross-coupled inverters. This difference in voltage levels on the bit line
114
and {overscore (bit)} line
116
is detected by the differential detector (not shown), and an appropriate logic “0” or logic “1” value is produced by the differential detector, corresponding to the logic state of the selected memory cell. Thus, the use of a differential detector allows the data to be detected on the bit lines without the bit lines being charged to full logic 0 or 1 levels.
Precharging the bitlines also increases the speed of read or write operations since data that was previously read or written may remain on the bit lines. In addition to slowing down the subsequent read or write, the pre-existing data may corrupt the new data. Thus, precharging to a level between the supply voltage and ground may also prevent errors in reading or writing to the memory cell.
However, precharge circuitry adds both complexity and size to the memory. Incorporating precharge circuitry utilizes critical area that can be used for other purposes and adds complexity to the design.
Accordingly, it is desirable to have an SRAM memory that does not require precharge circuitry so that the physical size and/or the complexity of the memory can be minimized or valuable area can be used for other purposes.
SUMMARY
In accordance with one aspect of the present invention, a pull-up device drives word lines in a static random access memory (SRAM) during a read operation. The pull-up devices control the rise time to charge the word lines to their full voltage levels during the read operation. By slowly charging the word lines, data stored in the SRAM memory cells are not corrupted or destroyed by changing states as the bitline charge is coupled too quickly to the SRAM cell. The present invention eliminates the need for separate precharge circuitry, which reduces the complexity and size of the SRAM memory.
In one embodiment, the memory includes an SRAM cell f

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