Static random access memory (SRAM) cells

Details Static random access memory (SRAM) cells Static random access memory (SRAM) cells

2011-03-01

2011-03-01

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000, C365S063000, C365S072000

Reexamination Certificate

active

07898894

ABSTRACT:
The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless, the SRAM cell of the present invention typically includes separate/decoupled write word and read word lines, a pair of cross-coupled inverters, and a complimentary pair of pass transistors that are coupled to the write word line. Each set of stacked transistors implemented within the SRAM cell has a transistor that is coupled to a bit line as well as the read word line.

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