Static random access memory including stress test circuitry

Details Static random access memory including stress test circuitry Static random access memory including stress test circuitry

1991-12-26

1994-01-04

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36518911, 371 211, G11C 700

Patent

active

052766470

ABSTRACT:
SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

REFERENCES:
patent: 4543647 (1985-09-01), Yoshida
patent: 4802137 (1989-01-01), Okuda et al.
patent: 4958326 (1990-09-01), Sakurai
patent: 4999813 (1991-03-01), Ohtsuka et al.
patent: 5132929 (1992-07-01), Ochii
patent: 5177745 (1993-01-01), Rozman

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