Static random access memory having leakage reduction circuit

Details Static random access memory having leakage reduction circuit Static random access memory having leakage reduction circuit

2005-04-05

2005-04-05

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S230060, C365S206000

Reexamination Certificate

active

06876571

ABSTRACT:
A static random access memory (SRAM) is provided that includes a logic circuit coupled to a column select signal line and a leakage reduction circuit coupled to the logic circuit and a bit line pair of a column. The logic circuit may control the leakage reduction circuit so as to reduce leakage through a column select device that is not selected.

REFERENCES:
patent: 6327215 (2001-12-01), Ternullo et al.
patent: 6560139 (2003-05-01), Ma et al.
patent: 6678202 (2004-01-01), Scott
patent: 20020141265 (2002-10-01), Somasekhar et al.
Azzez J. Bhavnagarwala et al., “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability”, IEEE Journal of Solid-State Circuits, vol. 36, No. 4, Apr. 2001, pp. 658-665.
Ken'ichi Agawa et al., “A Bitline Leakage Compensation Scheme for Low-Voltage SRAMs,” IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 726-734.

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