Static random access memory having column decoded bit line bias

Details Static random access memory having column decoded bit line bias Static random access memory having column decoded bit line bias

1989-06-23

1991-01-15

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including signal clamping

365154, 365203, G11C 700

Patent

active

049858645

ABSTRACT:
In a static random access memory formed by an array of rows and columns of memory cells, separate bit lines convey a data bit to or from memory cells of separate columns. Gates controlled by an input row address connect only a single memory cell of each column to the bit lines of the column so that only a single memory cell of the column transmits or receives a data bit on the bit line. Gates controlled by a column address connect the bit lines of only a single column to data input and output circuits. During a write cycle, the memory cell connected to each bit line pair attempts to bias the bit line pair in accordance with the state of its stored data bit, but bit line pairs of non-addressed columns are coupled to a voltage source to prevent a row addressed memory cell of that column from strongly biasing the bit lines. Following the end of a write cycle, a precharge circuit temporarily clamps all bit lines to the voltage source to precharge bit line capacitance. The selective clamping of bit lines of non-addressed columns during the write cycle minimizes a charging current spike produced by the precharge circuit.

REFERENCES:
patent: 4161040 (1979-07-01), Satoh
patent: 4829477 (1989-05-01), Suzuki et al.
Kim C. Hardee and Rahul Sud, "A Fault-Tolerant 30 ns/375 mW 16K X 1 NMOS Static RAM", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. '81.

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