Static random access memory device having a single bit line conf

Details Static random access memory device having a single bit line conf Static random access memory device having a single bit line conf

1995-06-06

1996-11-05

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36523006, 365226, 365204, G11C 1140

Patent

active

055724698

ABSTRACT:
A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

REFERENCES:
patent: 4984201 (1991-01-01), Sato et al.
patent: 5353257 (1994-10-01), Yanagisawa et al.
patent: 5359839 (1994-11-01), Igarashi
patent: 5361237 (1994-11-01), Chishiki
"16K CMOS/SOS Asynchronous Static RAM", Roger G. Stewart et al., Digest of Technical Papers, 1979, IEEE International Solid-State Circuits Conference, pp. 104-105, 286.
"A Dynamic Three-State Memory Cell for High-Density Associative Processors", Frederick P. Herrmann et al., 1990 Symposium on BLSI Circuits, pp. 73-74.
"A Novel Cell Structure for 4M Bit Full Feature EEPROM and Beyond", N. Ajika et al., Techical Digest, International Electron Devices Meeting 1991, pp. 11.1.1-11.1.4.
"Non-Inverting Conditions of a Flipflop Circuit", Institute of Electronics, Information and Communication Engineers of Japan, Showa 54, vol. 2, pp. 2-185.

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