Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-13
2002-07-09
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S314000, C365S063000, C365S154000, C365S190000, C365S203000, C365S205000, C365S207000, C365S208000, C365S233100
Reexamination Certificate
active
06417549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a static random access memory device (SRAM) which can be manufactured by a CMOS standard logic manufacturing process and a method for manufacturing the same.
2. Description of the Related Art
Static random access memories (SRAMs) are easy to use and operate faster compared to dynamic random access memories (DRAM). For these reasons, the SRAMs have been used typically as a cache memory or a system memory in terminals. Recently, a development tendency of semiconductor devices towards high performance and composite functionality has raised use of SRAM embedded logic products, in which SRAMs and logic products are merged in one chip.
Referring to
FIG. 1
, an equivalent circuit diagram of a unit memory cell of a general SRAM device is shown. As shown in
FIG. 1
, the SRAM cell is composed of two access transistors Q
1
and Q
2
and a flip-flop circuit including a pair of CMOS inverters. The first inverter is composed of transistors Q
5
and Q
3
, and the second inverter is composed of transistors Q
6
and Q
4
. SRAM cells are classified into one of three types including a resistor type SRAM, a thin film transistor type SRAM and a pull CMOS type SRAM, according to the type of load transistors, i.e., transistors Q
5
and Q
6
, of the flip-flop. Recently, the increasing need for low power supply voltage and high-speed products has raised interest in the full CMOS type SRAM.
However, as shown in
FIG. 1
, the full CMOS SRAM requires six transistors Q
1
through Q
6
and twelve nodes C
1
through C
12
to constitute one memory cell. Thus, it has high cell area, resulting in the disadvantage of less integration density, compared to the other two types of cells, which require only four transistors.
In
FIG. 1
, the first access transistor Q
1
and the second access transistor Q
2
have their gates connected respectively via the nodes C
9
and C
10
to a word line WL, and their sources connected respectively via the nodes C
7
and C
8
to first and second bit lines BL
1
and BL
2
. The first CMOS inverter, which is composed of the first load transistor Q
5
and the first drive transistor Q
3
, has an input connected via nodes C
4
and C
2
, respectively, to the output of the second CMOS inverter and the drain of the second access transistor Q
2
, and an output connected via the nodes C
1
and C
3
, respectively, to the drain of the first access transistor Q
1
and the input (i.e., the node C
6
) of the second CMOS inverter. The second CMOS inverter, which is composed of the second load transistor Q
6
and the second drive transistor Q
4
, has an input (i.e., the node C
6
) connected via the nodes C
3
and C
1
, respectively, to the output of the first CMOS inverter and the drain of the first access transistor Q
1
, and an output connected via the nodes C
2
and C
4
, respectively, to the drain of the second access transistor Q
2
and the input (i.e., the node C
5
) of the first CMOS inverter. Also, the drains of the first and second load transistors Q
5
and Q
6
are connected via the node C
12
to a first power supply voltage Vcc, and the sources of the first and second drive transistors Q
3
and Q
4
are connected via the node C
11
to a second power supply voltage Vss.
FIG. 2
is a sectional view showing part of the conventional full CMOS type SRAM cell of
FIG. 1
, in which the input of the first CMOS inverter (the node C
5
formed on the gate of the first load transistor Q
5
), the source
16
of the second load transistor Q
6
and the drain
18
of the second access transistor Q
2
(which shares the drain
18
with the second drive transistor Q
4
) are connected via the nodes C
4
and C
2
by a local interconnection line
22
.
In
FIG. 2
, reference numeral
10
represents a semiconductor substrate, reference numeral
12
represents a field oxide layer, reference numeral
14
represents the gate of the first load transistor Q
5
, reference numeral
16
represents the source of the second load transistor Q
6
, reference numeral
18
represents the drain of the second access transistor Q
2
and the second drive transistor Q
4
, reference numeral
20
represents an insulating layer, reference numeral
22
represents the local interconnection line, reference numeral
24
represents a first interlayer dielectric (ILD) film, reference numeral
26
represents a word line, reference numeral
28
represents a second ILD film, reference numeral
30
represents a power supply line, reference numeral
32
represents a third ILD film, and reference numeral
34
represents a bit line.
The input (refer to the gate
14
of the first load transistor Q
5
) of the first CMOS inverter is connected via the first local interconnection line, which is formed of a bilayer including a titanium (Ti) layer and a titanium nitride (TiN) layer, to the source
16
of the second load transistor Q
6
and the drain
18
of the second access transistor Q
2
and the second drive transistor Q
4
. The input (not shown) of the second CMOS inverter is connected via a second local interconnection line (not shown) to the source (not shown) of the first load transistor Q
5
and the drain (not shown) of the first access transistor Q
1
and the first drive transistor Q
3
.
The word line
26
is connected to the gates of the first and second access transistors Q
1
(not shown) and Q
2
. The power supply line
30
and the bit lines are formed in different layers with a metal interconnection. In
FIG. 2
, the power supply line
30
extends in the lateral direction and the bit line
34
extends in the vertical direction.
Merging the SRAM cell of
FIG. 2
with a logic device requires additional processes based on a general CMOS standard logic manufacturing process, thereby increasing the manufacturing cost due to the need for additional photolithography processes and making the overall process complicated. In particular, as shown in
FIG. 2
, for the connection between the input of the first CMOS inverter and the output of the second CMOS inverter, and between the output of the second CMOS inverter and the input of the first CMOS inverter, the conventional full CMOS type SRAM requires the formation of the local interconnection line having a bilayer structure including, for example, a Ti layer and a TiN layer, in addition to the general CMOS standard logic manufacturing process, and in turn additional masks therefor.
The word line
26
is formed of polyslicon, which is also used in forming the gate of the load transistor Q
5
. However, similar to the formation of the local interconnection line, additional processes in addition to the general CMOS standard logic manufacturing process must be carried out for the word line
26
. Two more masks, one for the word line and the other for the contact hole connecting the word line and a transistor, are required, rendering the manufacturing process complicated.
Also, when the SRAM cell of
FIG. 2
is merged with a logic device without performing additional processes, the size of the SRAM cell increases beyond a desired size.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a static random access memory (SRAM) device which can be manufactured by standard CMOS logic manufacturing processes without the need for additional masks or processes, wherein an increase in cell size is minimized.
Another object of the present invention is to provide a method for manufacturing an SRAM device by standard CMOS logic manufacturing processes without the need for additional masks or processes, wherein an increase in cell size is minimized.
The first object is achieved by a SRAM device comprising: first and second access transistors each having a gate connected to a word line and a source connected to a bit line. The SRAM also includes a first inverter including a first drive transistor and a first load transistor and a second inverter including a second drive transistor and a seco
Mills & Onello LLP
Wojciechowicz Edward
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