Static random access memory device

Details Static random access memory device Static random access memory device

2000-11-09

2003-05-06

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S382000, C257S904000, C257S921000

Reexamination Certificate

active

06559510

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device such as SRAM (Static Random Access Memory), and a method of manufacturing the same.
Conventionally, a soft error (hereinafter, may be abbreviated as SER) caused by an &agr;-ray often takes place with high-integration of a SRAM device in a semiconductor device of the type as described.
More specifically, when a memory cell is reduced in size in order to highly integrate the SRAM device, a current per a unit memory cell is reduced. On the other hand, the &agr;-ray emitted from natural uranium or the like is irradiated into a semiconductor memory device.
Herein, it is noted that the natural uranium is slightly contained in a ceramic package or a cover for sealing the semiconductor memory device.
Thereby, a large number of electron-hole pairs are generated in a substrate. Consequently, the electron being generated moves in the substrate and destroys information (namely, electric charge) stored in the memory cell. This results to an error operation of the semiconductor memory cell.
Referring to
FIG. 1
, description will be made about a basic structure of a high-resistance load type memory cell serving as a main part of the related SRAM device.
The SRAM device includes a pair of transfer transistors ST
1
and ST
2
, a pair of driving transistors DT
1
and DT
2
, and a pair of load resistors L
1
and L
2
.
In the transfer transistor ST
1
, one terminal (source or drain) is connected to a bit line BL
1
while the other terminal (source or drain) is connected to a node N
1
. Further, the gate electrode terminal is connected to a word line WL
1
.
In the transfer transistor ST
2
, one terminal (source or drain) is connected to a bit line BL
2
while the other terminal (source or drain) is connected to a node N
2
. Further, the gate electrode terminal is connected to a word line WL
2
.
In the driving transistor DT
1
, one terminal (source or drain) is connected to a reference voltage Vss while the other terminal (source or drain) is connected to the node N
1
. Further, the gate electrode terminal is connected to the node N
2
.
In the driving transistor DT
2
, one terminal (source or drain) is connected to a reference voltage Vss while the other terminal (source or drain) is connected to the node N
2
. Further, the gate electrode terminal is connected to the node N
1
.
In the load resistor L
1
, one terminal is connected to a power supply voltage Vcc while the other terminal is connected to the node N
1
.
In the load resistor L
2
, one terminal is connected to the power supply voltage Vcc while the other terminal is connected to the node N
2
.
Further, a capacitor C
1
is coupled to the node N
1
while a capacitor C
2
is coupled to the node N
2
.
For example, a NMOS may be used as each of the transfer transistors ST
1
, ST
2
, and the driving transistors DT
1
, DT
2
.
Subsequently description will be made about a SER resistance in such high-resistance load type memory cell.
In the case of the resistance load type memory cell, the SER resistance is generally determined in dependence upon a current IL flowing through the load resistor L
1
, L
2
and node capacitance C
1
, C
2
.
When the node N
1
is put into a high state and a voltage is equal to V
1
h in the memory cell, the current IL flowing through the load resistor L
1
and the node capacitance C
1
has the following relationship with the SER resistance.
Namely, in the case where the bit line BL
1
is put into the power supply voltage Vcc, when the transfer transistor ST
1
is turned on, the voltage V
1
h of the node N
1
is reduced with about a threshold voltage Vt of the transfer transistor ST
1
from the power supply voltage Vcc to become Vcc−Vt.
Under this circumstance, if the current sufficiently flows through the load resistor L
1
from the power supply voltage Vcc, the voltage V
1
h is more increased to the power supply voltage Vcc.
In such a memory cell, when the transfer transistor ST
1
is turned on and the voltage V
1
h is reduced from the power supply voltage Vcc to Vcc−Vt, the probability of the occurrence of the decrease in the voltage V
1
h, in which the voltage is reduced from the power supply voltage Vcc to the Vc−Vt, may be lowered as the node capacitance C
1
becomes higher.
In addition, such a time that the voltage V
1
h further restores to the power supply voltage Vcc by the power supply voltage Vcc of the power supply becomes rapider, as the current IL flowing through the load resistor L
1
is higher and as the node capacitance C
1
is higher.
Hereinafter, description will be made about a method of manufacturing the high resistance load memory cell with reference to
FIGS. 2 through 7
.
Herein, only a region around the node N
1
of the memory cell in
FIG. 1
is illustrated in
FIGS. 2 through 7
, and the illustration of the peripheral circuit portion is omitted.
Referring to
FIG. 2
, a thick device isolation silicon oxide film
2
is formed to a thickness of 400 nm by the use of Local Oxidation of Silicon (LOCOS) method on a principal surface of a silicon substrate
1
.
Thereafter, only region for forming a memory cell region, a transfer transistor, and a driving transistor (namely, NMOS) are opened by the use of the photolithography technique.
Subsequently, impurity (boron) is implanted so as to form a P-type well region
21
by the ion-implanting technique.
In this event, the ions are implanted within a concentration range between 1×10
13
and 2×10
13
[cm
−2
] and within an accelerating voltage range between 250 and 350 [Kev].
Although not illustrated, the ions are implanted to form the device isolation region at the same time, and a P-type impurity region is formed under the device isolation silicon oxide film
2
. Further, the ions are also implanted so as to control the voltage Vt.
Thereafter, the silicon substrate
1
is thermally oxidized to form a gate silicon oxide film
3
to a thickness of about 8 nm. Successively, a polysilicon film is deposited to a thickness of about 100 nm of the gate silicon oxide film
3
by the use of CVD technique.
Subsequently, compound (namely, silicide) between Ti or W serving vas a high-melting point metal and silicon is deposited to a thickness of about 100 nm by thermally diffusing phosphorus to form a polyside.
Further, the gate electrode
4
is patterned by the use of the photolithography technique.
Referring to
FIG. 3
, only a region for forming the memory cell region, the transfer transistor and the driving transistor (namely, NMOS) is opened by the use of the photolithography technique.
Thereafter, impurity (phosphorus) is implanted in a self-alignment. manner using the gate electrode
4
as a mask by the ion implanting technique to form an N-type low concentration impurity region
5
.
In this case, the ions are implanted within the concentration range between 1×10
13
and 3×10
13
[cm
−2
] and within the accelerating voltage range between 15 and 25 [Kev].
Next, the silicon oxide film
6
is formed within the thickness range between 100 and 150 nm on the device isolation silicon oxide film
2
, the gate silicon oxide film
3
, and the gate electrode
4
by the use of the CVD technique.
Successively, referring to
FIG. 4
, the silicon oxide film
6
is etched-back by the use of the etching technique to form a sidewall silicon oxide film
7
at the sidewall of the gate electrode
4
.
Thereafter, only a region for forming the memory cell region, the transfer transistor and the driving transistor (namely, NMOS) is opened by the use of the photolithography technique.
Subsequently, impurity (phosphorus) is implanted in a self-alignment manner using the gate electrode
4
and the sidewall silicon oxide film
7
as a mask by the ion implanting technique to form a N-type high concentration impurity region
8
.
In this case, the ions are implanted within the concentration range between 1×10
15
and 5×10
15
[cm
−2
] and within the accelerating voltage range between 30 and 40 &

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