Static random access memory cell with single logic-high voltage

Details Static random access memory cell with single logic-high voltage Static random access memory cell with single logic-high voltage

1993-01-08

1994-04-05

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365190, 365202, G11C 1100

Patent

active

053011473

ABSTRACT:
A static random access memory cell according to the present invention comprises first and second cross-coupled inverters. The first inverter includes a first P-Channel MOS transistor having a source connected to a first power supply node, a gate, and a drain, and a first N-Channel MOS transistor having a drain connected to the drain of the first P-Channel MOS transistor and forming an output node, a gate, and a source connected to a fixed power supply potential. The second inverter includes a second P-Channel MOS transistor having a source connected to the first power supply node, a gate, and a drain, and a second N-Channel MOS transistor having a drain connected to the drain of the second P-Channel MOS transistor, a gate, and a source connected to the fixed power supply potential. The gates of the first P-Channel and N-Channel MOS transistors are connected to the common drains of the second P-Channel and N-Channel MOS transistors and the gates of the second P-Channel and N-Channel MOS transistors are connected to the common drains of the first P-Channel and N-Channel MOS transistors to form the cross coupling connections. A pass transistor is connected between the output node of the memory cell and a bitline. Circuitry is provided to provide a first power supply potential during a read operation and a second power supply potential during a write operation to the first power supply node. The first power supply potential is higher than the second power supply potential.

REFERENCES:
patent: 4499560 (1985-02-01), Brice
patent: 4750155 (1988-06-01), Hsieh
patent: 4872141 (1989-10-01), Plus et al.

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