Static information storage and retrieval – Systems using particular element – Flip-flop
Patent
1993-09-24
1995-03-07
LaRoche, Eugene R.
Static information storage and retrieval
Systems using particular element
Flip-flop
257367, 257903, 257904, 365156, 365190, G11C 1140
Patent
active
053964543
ABSTRACT:
A memory cell includes gated diodes as load elements. For example, the memory cell includes a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor, a fourth transistor, a first gated diode and a second gated diode. The first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line. The second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line. The third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor. The fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor. The first gated diode includes a first end connected to the power line and a second end connected to the second end of the first transistor. The second gated diode includes a first end connected to the power line and a second end connected to the first end of the second transistor.
REFERENCES:
patent: 5046044 (1991-09-01), Houston et al.
T. Ohzone, T. Hirao, K. Tsuji, S. Horiuchi, and S. Takayanagi, A 2K.times. 8-Bit Static MOS RAM with a New Memory Cell Structure, IEEE J. Solid-State Circuits, vol. SC-15, Apr. 1980, pp. 201-205.
N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi and T. Shimada, A 16ns 2K .times. 8 Bit Full CMOS SRAM, IEEE Journal of Solid-State Circuitsvol. SC-10, No. 5, Oct. 1984, pp. 552-556.
T. Y. Chan, J. Chen, P. K. Ko and C. Hu, The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling, Digest of IEDM, 1987, pp. 718-721.
T. Endoh, et al., An Accurate Model of Subbreakdown Due to Band-to-Band Tunneling and Some Applications, IEEE Transactions on Electron Devices, vol. 37, No. 1, Jan. 1990, pp. 290-295.
Glembocki Christopher R.
LaRoche Eugene R.
VLSI Technology Inc.
Weller Douglas L.
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