Static random access memory cell having graded channel metal oxi

Static information storage and retrieval – Systems using particular element – Flip-flop

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365156, G11C 1100

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active

058869212

ABSTRACT:
An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).

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"Field Effect-Transistor With Asymmetrical Structure", Codella et al., United States Statutory Invention Registration No. H986, Published Nov. 5, 1991, U.S. Class 437, Subclass 41, Application Filing Date Jun. 9, 1989.

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