Static random access memories and access methods thereof

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S189020, C365S189040, C365S190000, C365S196000, C365S205000

Reexamination Certificate

active

07983073

ABSTRACT:
A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other.

REFERENCES:
patent: 7583543 (2009-09-01), Sumitani
patent: 2008/0074932 (2008-03-01), Sumitani
“Wordling & Bitling Pulsing Schemes for Improving SPAM Cell Stability in Low-Vcc 65nm CMOS Designs”, Muhammad et al., Symposium on VLSI Ciscuits Digest of Technical Papers, IEEE, 2006.
“6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM”, R. Joshi, et al, Symposium on VLSI Circuits Digest of Technical Papers, 2007.

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