Static ram with reduced power consumption

Details Static ram with reduced power consumption Static ram with reduced power consumption

1997-04-10

1998-10-06

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

36518901, G11C 1300

Patent

active

058187758

ABSTRACT:
The invention relates to a memory comprising a matrix of memory cells; a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows of the matrix; a dummy bit line having an equivalent load as bit lines associated to columns of the matrix and which is discharged by a dummy memory cell when any row is selected; and circuitry for precharging the bit lines and the dummy bit line when no row is selected, and enabling said gates for transmission of the selection outputs of the row decoder in response to a clock signal. Each gate has an input coupled to the dummy bit line such that the gate is disabled as soon as the dummy bit line has discharged to a switching threshold of the gate.

REFERENCES:
patent: 5132931 (1992-07-01), Koker
patent: 5394354 (1995-02-01), Watabe et al.
patent: 5408438 (1995-04-01), Tanaka et al.

Affiliated with

Also associated with

Rating

Static ram with reduced power consumption does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Static ram with reduced power consumption, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Static ram with reduced power consumption will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-86488