Static RAM with optimized timing of driving control signal...

Details Static RAM with optimized timing of driving control signal... Static RAM with optimized timing of driving control signal...

2002-01-08

2003-04-29

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S210130

Reexamination Certificate

active

06556472

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static RAM, and more particularly to a clock-synchronized SRAM with optimized timing of a driving control signal such as for the sense amplifier.
2. Description of the Related Art
Static RAM (hereinafter “SRAM”) comprises a latch circuit having cross-connected CMOS inverters in the memory cell and is a high-speed semiconductor memory which can retain stored data so long as power is applied. Data is continuously held by the latch circuit of the memory cell, making unnecessary periodic refresh operations such as in DRAM. Clock-synchronized SRAM is one of the types of high-speed SRAM developed in recent years. In this clock-synchronized SRAM, the address and control signal are supplied in synchronization with a clock, the internal circuitry operates according to the timing of the clock, and data are output after a prescribed access time from the supply of the clock.
Non-clock-synchronized SRAM does not have the clock supplied from outside, and instead, the internal circuitry is started upon the detection of a change of the input address.
The internal operations of SRAM are generally as follows. First, in the clock-synchronized type, an address input in synchronization with a clock is decoded and a word line is driven. With the driving of the word line, the memory cell drives a bit line and the voltage difference developed between bit lines is amplified by the sense amplifier. The data amplified by the sense amplifier are then output from the output buffer. When the reading operation is complete, the bit line pair and sense amplifier output pair are short circuited and precharged to the power supply voltage.
All of the operations above are controlled by a timing control signal generated by a timing control circuit. In particular, the sense amplifier enable signal is preferably generated at the shortest time after the bit line is driven by the memory cell and the prescribed voltage difference is developed between bit lines. The driving capability of the memory cell varies according to the process variation. Accordingly, the sense amplifier control signal is generated with a sufficient timing margin from the activation of the word line. Even if the driving capability of the memory cell varies into lower and the time at which the prescribed potential difference is developed between bit lines is delayed, the sense amplifier does not operate in error due to this timing margin.
The high-speed characteristics of SRAM are lost when sufficient margin is established in the timing of the bit line enable signal as discussed above. A proposed method for resolving this problem is a self-timing system wherein a dummy circuit, with a word line, memory cells, and bit lines, is provided and the sense amplifier enable signal is generated using this dummy circuit.
FIG. 1
shows a schematic of conventional SRAM using such a dummy circuit. In this example, the address Add and control signal Cont input in synchronization with the clock CK are decoded by the timing control circuit and decoder circuit
14
, and the timing signals EQB, CS, EQ, and OE are generated. The word line WL selected by the decoder circuit is driven by the word line driver
12
and selects a memory cell MC in the memory cell array
10
. In response thereto, the memory cell MC drives the bit line pair BL, BLX and the bit line pair selected by the column switch
18
is amplified by the sense amplifier
20
. The sense amplifier output SO, SOX is latched by the output latch circuit
24
at the time of the output enable signal OE and output to the output buffer
26
through the output lines OL, OLX, and the output data Dout are generated. After that, the bit line pair is short circuited by the bit line equalizing circuit
16
at the time of the bit line equalizing signal EQB and precharged to the power source voltage. In the same way, the sense amplifier output So, SOX is also short circuited and precharged at the time of the equalizing signal EQ. When writing, the input data Din is input to the input circuit and write amplifier
28
, and the selected bit line pair is driven from the write amplifier.
In this prior art, a dummy word line DWL is provided separately from the word line WL in the memory cell array
10
; the dummy memory cells DMC are provided separately from the regular memory cells MC, and the dummy bit line pair DBL, DBLX is provided separately from the regular bit line pair BL, BLX. A loading dummy cell DMCW is provided on the dummy word line DWL and a loading dummy cell DMCB is provided on the dummy bit line pair DBL, DBLX. Accordingly, the dummy word line DWL is driven when the regular word line WL is driven and, at the time when the prescribed voltage difference is generated across the regular bit line pair, the same voltage difference is generated across the dummy bit line pair DBL, DBLX. Consequently, the SE timing circuit
30
generates the sense amplifier enable signal SE in response to the voltage difference on the dummy bit line pair DBL, DBLX and can thereby start the sense amplifier
20
at the optimum timing.
Even when the driving capability of the memory cell varies because of the process variation, the sense amplifier enable signal SE can be generated at the optimum timing corresponding to those process variation because the same variation occur in the dummy memory cell DMC.
A problem of the prior art discussed above is that since the dummy circuit, comprising a dummy word line DWL, a dummy memory cell DMC, and dummy bit line pair DBL, DBLX, is accessed each cycle, the reliability of transistors and wiring in the dummy circuit is lower than that of the regular circuit, comprising a word line, memory cells, and bit line pair. For example, if there are 512 word lines WL in the memory cell array
10
, the probability that a regular word line WL will be operating is 1/512. On the other hand, because the dummy word line DWL is accessed each cycle, the probability of the driving operation is 1. The dummy word line is driven at a high frequency and consequently, the transfer gate transistors in the dummy memory cell controlled by the dummy word line is controlled in a conductive state every cycle by the driving of the dummy word line. Because of this control, the transfer gate transistors have decreased its driving capability because of hot carrier deterioration and the like so that the timing of the sense amplifier enable signal SE generated by the dummy circuit will be delayed.
Furthermore, the prior art discussed above results in greatly increased power consumption because the dummy circuit operates every cycle and the dummy word line is driven separately from the regular word line. In effect, during normal operations, the regular word line WL is driven along with the dummy word line DWL, and as a result the power consumption increases.
FIG. 2
shows the constitution of another conventional SRAM using a dummy circuit. The same reference numbers are used as in FIG.
1
. In this prior art, a dummy word line is not provided and all the regular word lines WL are connected to the dummy memory cells DMC provided on the left side of the memory cell array
10
. Consequently, the dummy memory cells DMC are positioned along the dummy bit lines DBL, DBLX and are disposed in the same way as the regular memory cells MC.
Because the dummy word line is omitted from this example, the increase in power consumption can be suppressed by a corresponding degree. Moreover, the decrease in reliability can be prevented because the dummy memory cells DMC are not accessed every cycle.
However, because every word line is connected to a dummy memory cell, the dummy memory cells DMC must be provided at the same pitch as the regular memory cells MC. Even if the dummy bit line pair DBL, DBLX is driven by a plurality of dummy memory cells DMC, the driving operation cannot be made faster than that of the regular bit line pair BL, BLX and it becomes difficult to provide optimum timing of the sense amplifier enable signal SE. In effect, in order to generate t

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