Static RAM with non-volatile back-up storage and method of opera

Static information storage and retrieval – Systems using particular element – Flip-flop

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357 23, 365185, G11C 1140

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active

044208219

ABSTRACT:
An FET semiconductor memory array composed of cells each including a flip-flop static memory element and a non-volatile memory element including a dual gate FET. One of the gates of the FET is a floating gate which is separated from the channel of the dual gate FET by the same thin oxide layer that separates the other of the gates from the channel of the dual gate FET. A segment of DEIS (Dual Electron Injection Stack) is disposed between the floating gate and an upper control electrode. A data node of the flip-flop circuit is connected to a node of the non-volatile element through another FET. A capacitor is connected between the floating gate and the latter node.

REFERENCES:
patent: 3676717 (1972-07-01), Lockwood
patent: 4207615 (1980-06-01), Mar
patent: 4388704 (1983-06-01), Bertin et al.
Electronics, Oct. 11, '79, R. Klein et al., "5-Volt-Only, Nonvolatile RAM owes it all to Polysilicon".
ISSCC, Feb. 18, '81, WAM 3.2: A Dual-Gate Floating-Gate FET Device, H. Kotecha et al.
ISSCC 81, Feb. 19, '81, THPM 12.1: A Single 5V Supply Nonvolatile Static RAM, J. Drori et al.
IEEE Trans. on Electron Devices, vol. ED-28, No. 9, Sep. '81, D. DiMaria et al., "Dual Electron Injector Structure Electrically . . . ".
IBM Technical Disclosure Bulletin-vol. 24, No. 73, Dec. 1981, pp. 3691-3692.

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