Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
1995-07-31
2001-06-12
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000
Reexamination Certificate
active
06246605
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static RAM, and more particularly to a split word line type static RAM with thin film transistor (TFT) load elements.
2. Description of the Related Art
Memory cells for conventional static type RAMs will now be described with reference to the layout diagram in FIG.
7
and the circuit diagram in FIG.
8
.
As is shown in the diagram, a flip-flop
14
is formed within a memory cell
11
from a first inverter
12
and a second inverter
13
. A first word transistor
15
and a second word transistor
16
are then connected to this flip-flop.
A gate electrode
21
for a first driver transistor
17
constructed in the first inverter
12
and a gate electrode
22
for a second driver transistor
18
constructed in the second inverter
13
are arranged point symmetrically about a point O. A word line
23
including the gate electrode for the for the first word transistor
15
and a word line
24
including the gate electrode for the second word transistor
16
are also arranged symmetrically about the same point
0
. In addition to this, the diffusion layer regions
25
and
26
for the first and second word transistors
15
and
16
and the diffusion layer regions
27
and
28
for the respective first and second driver transistors
17
and
18
which regions
27
and
28
are connected to the regions
25
and
26
, respectively, are also arranged symmetrically about the same point
0
.
Also, a gate terminal
29
for the first load element
19
(as this load element is a TFT, it will herein be referred to as the first TFT) within the first inverter
12
and a gate electrode
30
for the second load element
20
(as this load element is also made from TFT, it will herein be referred to as the second TFT) within the second inverter
13
are also arranged point symmetrically about this point
0
within the region for the same memory cell
11
.
Further, a channel region
31
of the first TFT
19
, a channel wiring
41
which is connected to the channel region
31
, a channel region
32
for the second TFT
20
, and the separate channel wiring
42
which is connected to the channel region
32
are arranged so as to be symmetrical about the central point
0
. In addition, the channel wiring
41
is laid on the word line
24
, whereas the other channel wiring
42
is laid on the word line
23
.
As is shown in a schematic cross-sectional diagram in
FIG. 9
, in the split word line type static RAM
5
with TFT load elements there is a contact hole
110
used for bit contact which, in addition to being in between the memory cells
11
and
111
, is also in between the first word line
23
for the memory cell
11
and a second word line
112
for the memory cell
111
. A bit line
120
is then connected to the diffusion layer
34
of the first word transistor
15
via a plug
115
which is formed in the contact hole
110
.
However, with static RAMs having the above structure, there are two pieces of channel wiring connected within one memory cell region. As a result, it is not possible to secure a region for forming a capacitor (cross coupled capacitor) with the polysilicon film which makes up the gate electrode of the TFT and the polysilicon layer which makes up the channel region of the same TFT as a counter measure against soft errors, which makes the forming of such a capacitor very difficult.
If such a capacitor having a sufficient capacity is to be formed, additional layers have to be formed to make up this capacitor.
Also, with the connection of the diffusion layer of the word transistor and the bit line in the above structure, the aspect ratio for the contact hole usually becomes large since the contact hole is formed by self-alignment with a stepped portion in the first layer polysilicon film forming the first and second word lines. It is then very difficult to embed and form the bit line with a good coverage into the contact hole. The reliability of the wiring for the bit line would be therefore degraded.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a static RAM where a region can be secured for forming a capacitor to be used as a countermeasure against soft errors, where a sufficiently long TFT channel length can be ensured, and where the bit contact reliability is high.
In order to attain this and other objects, according to present invention, there is provided a static RAM which has the following features:
A pattern for a first driver transistor and a pattern for a second driver transistor included in this RAM are therefore arranged so as to be symmetrical about a point with each other. A pattern for a first word transistor and a pattern for a second word transistor are also arranged symmetrically about the point, and a pattern for a first load element and a pattern for a second load element are arranged asymmetrically.
For example, the first and second load elements are thin film transistors, the channel region of the first load element then extends outwardly from the memory cell, and the channel region of the second load element are connected via channel wiring to the memory cell region. A capacitor can also be formed in least one part of the extended channel region.
Also, a bit line is connected to the diffusion layer of one of the word transistors via a wire connected to and overlapping this word transistor and a bit contact formed on this wire.
In the static RAM having the aforementioned structure, by having the patterns for each of the first and second driver transistors and the patterns for each of the first and second word transistors arranged so as to be reciprocally point-symmetrical, and by having the patterns for first and second load elements arranged so as to be asymmetrical, the channel region for, for example, the first TFT, can be extended outwards from the memory cell region. It is also then possible to form a capacitor as a counter measure against, for example, soft errors, on at least one part of the extended channel region.
By connecting a bit line to a diffusion layer for one of the word transistors via a wiring connected to this word transistor and a bit contact part which is formed on this wiring, the aspect ratio for the bit contact part can be reduced.
REFERENCES:
patent: 4396996 (1983-08-01), Oldham
patent: 4570237 (1986-02-01), Nagayoshi
patent: 4833644 (1989-05-01), Plus
patent: 4841481 (1989-06-01), Ikeda
patent: 5018102 (1991-05-01), Houston
patent: 5241204 (1993-08-01), Kayama
patent: 5438537 (1995-08-01), Sasaki
Ishida Minoru
Okamoto Yutaka
Sonnenschein Nath & Rosenthal
Sony Corporation
Zarabian A.
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