Static ram with high speed, low power reset

Details Static ram with high speed, low power reset Static ram with high speed, low power reset

1988-05-26

1990-05-22

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

365154, G11C 700

Patent

active

049282662

ABSTRACT:
A static memory device is disclosed having an array of static memory cells, each memory cell having first and second cross-coupled inverters. All of the memory cells have distinct power voltage connections to the first and second inverters of each memory cell. When a reset signal occurs, the device's reset apparatus generates a voltage imbalance on the power voltage connections so that distinct voltage levels are applied to the first and second cross-coupled inverters of each memory cell. The voltage imbalance causes all of the memory cells in the array to be set into a predetermined state. In a preferred embodiment, the power voltage connections include a common high voltage power connection to all of the memory cells and distinct low voltage power connections to the first and second inverters of each memory cell. The reset apparatus applies a higher voltage potential on the low voltage power connection to the first inverters than the voltage potential applied on the low voltage power connection to the second inverters of each memory cell. As a result all memory cells are set into a state in which the internal storage nodes of the first inverters retain a higher voltage than the internal storage nodes of the second inverters. The memory cells are reset at very high speed and very low power, enabling use of a short reset pulse and a momentary power voltage imbalance to reset all of the cells in a memory device.

REFERENCES:
patent: 4780847 (1988-10-01), Ito

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