Static ram with common data line equalization

Details Static ram with common data line equalization Static ram with common data line equalization

1988-01-25

1989-10-31

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, 36518902, 36523002, G11C 700, G11C 2900

Patent

active

048781983

ABSTRACT:
A static random access memory having a plurality of pairs of common data out lines. A plurality of bit line pairs are coupled to each pair of common data out lines. The common data out lines are automatically equalized at the end of each memory access cycle, and the accessed bit lines are automatically equalized at the end of each write cycle. Thus, the process of equalizing the common data out lines is removed from the critical timing path for accessing the memory, which eliminates one of the primary problems in the use of address transition detection in static memory devices.

REFERENCES:
patent: 4355377 (1982-10-01), Sud et al.
patent: 4494221 (1985-01-01), Hardee et al.
patent: 4592026 (1986-05-01), Matsukawa et al.
patent: 4616344 (1986-10-01), Nogudi et al.
patent: 4638462 (1987-01-01), Rajeevakuman et al.
patent: 4646272 (1987-02-01), Takasugi
patent: 4764901 (1988-08-01), Sakurai
System Design/Integrated Circuits--Computer Design--vol. 22, No. 3, Mar. 1983, "The Chip That Refreshes Itself" by Fallin et al., pp. 111-122.

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