Static RAM with bit-line-charging transistor

Details Static RAM with bit-line-charging transistor Static RAM with bit-line-charging transistor

1984-01-31

1985-02-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365203, G11C 1140

Patent

active

044995598

ABSTRACT:
A static RAM, including a bit-line-charging transistor connected, in parallel to the load transistor, between each bit line and the power supply. These bit-line-charging transistors are controlled by a control signal generator circuit, which provides a timed pulse to their gates at the conclusion of each write cycle. The width of this timed pulse is selected such that bit lines which have been driven to a low level (e.g., zero volts) during a write cycle are rapidly recharged to the low level (e.g., 2.5 volts) to which they might have been driven during a read cycle. Thus, reverse readout operations (e.g., where a "1" is read immediately after a "0" has been written) no longer pose an obstacle to improving read operation speed, and speed and density can be improved.

REFERENCES:
patent: 4062000 (1977-12-01), Donnelly
patent: 4386419 (1983-05-01), Yamamoto

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