Static RAM semiconductor memory device having reduced memory

Details Static RAM semiconductor memory device having reduced memory Static RAM semiconductor memory device having reduced memory

2001-06-08

2003-03-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S390000, C365S063000

Reexamination Certificate

active

06538338

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor memory devices such as SRAMs (static random access memories).
2. Description of Related Art
SRAMs, one type of semiconductor memory devices, do not require a refreshing operation, and therefore have characteristics that can simplify a system in which they are incorporated and facilitate lower power consumption. For this reason, the SRAMs are prevailingly used as memories for hand-carry type equipment, such as cellular phones.
It is preferable for the hand-carry type equipment needs to be reduced in size. Therefore, the memory size of the SRAMs must be reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device that can reduce the size of memory cells.
In accordance with the present invention, a semiconductor memory device has a plurality of memory cells, each of the memory cells including a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor and a second transfer transistor. The memory cell includes first and second gate electrode layers, first and second drain—drain connection layers and first and second drain-gate connection layers. The first gate electrode layer includes gate electrodes of the first driver transistor and the first load transistor. The second gate electrode layer includes gate electrodes of the second driver transistor and the second load transistor. The first drain—drain connection layer connects a drain region of the first driver transistor and a drain region of the first load transistor. The second drain—drain connection layer connects a drain region of the second driver transistor and a drain region of the second load transistor. The first drain-gate connection layer connects the first drain—drain connection layer and the second gate electrode layer. The second drain-gate connection layer connects the second drain—drain connection layer and the first gate electrode layer. The drain—drain connection layers, the drain-gate connection layers and the gate electrode layers are provided in different layers, in plan view. The first and second gate electrode layers are positioned between the first drain—drain connection layer and the second drain—drain connection layer. The driver transistors of one of the memory cells does not commonly share a source region of the driver transistor of another of the memory cells.
The present invention is equipped with gate electrode layers that become gates of inverters, drain—drain connection layers that connect drains of the inverters, and drain-gate connection layers that connect gates of one of the inverters and drains of the other of the inverters. In accordance with the present invention, three layers (gate electrode layers, drain—drain connection layers, and drain-gate connection layers) are used to form a flip-flop. Accordingly, patterns in each layer can be simplified (for example, into linear patterns) compared to the case in which a flip-flop is formed using two layers. In this manner, in accordance with the present invention, since the patterns in each layer can be simplified, a miniaturized semiconductor memory device with its memory cell size being 4.5 &mgr;m
2
or smaller, for example, can be manufactured.
Also, in accordance with the present invention, in plan view, the first and second gate electrode layers are located between the first drain—drain connection layer and the second drain—drain connection layer. As a result, the source contact layer of the driver transistors can be disposed in the central area of the memory cell. Furthermore, a wiring that connects the source contact layer and the grounding line can be disposed in the same layer as the drain—drain connection layer and in the cell central area. Accordingly, the degree of freedom in forming the first and second drain-gate connection layers increases. This is also advantageous with regard to reducing the memory cell size. It is noted that, it the present invention, the “source contact layer” is a conduction layer that is used to connect a source region of the driver transistor and the wiring layer.
Also, in accordance with the present invention, a driver transistor of one memory cell does not commonly share a source region of a driver transistor of another memory cell. Accordingly, under any circumstances, only cell current for one-memory cell flows in the source region. As a result, in accordance with the present invention, the degree in the reduction of operation margin in a semiconductor memory device can be reduced, such that malfunctions of the semiconductor memory device can be prevented. This will be described in detail below.
In accordance with the present invention, in one of the memory cells, the first driver transistor commonly shares a source region of the second driver transistor. In accordance with the present invention, the first driver transistor and the second driver transistor commonly share a source region, such that the area of the source region can be made smaller. Accordingly, in accordance with the present invention, the semiconductor memory device can be reduced in size.
In accordance with the present invention, in one of the memory cells, a source region of the first and second driver transistors is located between the first gate electrode layer and the second gate electrode layer. In accordance with the present invention, in one memory cell, the first driver transistor can commonly share a source region with the second driver transistor.
The present invention also includes an auxiliary word line. The load transistors in one of the memory cells are arranged adjacent to each other in a direction in which the auxiliary word line extends, and do not commonly share a source region of the load transistors of another of the memory cells. In accordance with the present invention, since only cell current for one-memory cell flows in the source region of the load transistor, the degree in the reduction of operation margin can be reduced. As a result, malfunctions of the semiconductor memory device can be prevented. This will be described in detail below.
In accordance with the present invention, the first and second driver transistors are n-type, the first and second load transistors are p-type, and the first and second transfer transistors are n-type. The invention further includes first, second, third and fourth conduction layers. The first gate electrode layer, the second gate electrode layer and an auxiliary word line are located in the first conduction layer. The first drain—drain connection layer, the second drain—drain connection layer, a power supply line, a first contact pad layer, a second contact pad layer and a third contact pad layer are located in the second conduction layer. The first drain-gate connection layer, the second drain-gate connection layer, a main word line, a fourth contact pad layer, a fifth contact pad layer and a sixth contact pad layer are located in the third conduction layer. A first bit line, a second bit line and a grounding line are located in the fourth conduction layer. The auxiliary word line extends in a first direction. The power supply line connects to source regions of the first and second load transistors. The first contact pad layer is used to connect the first bit line and a source/drain region of the first transfer transistor. The second contact pad layer is used to connect the second bit line and a source/drain region of the second transfer transistor. The third contact pad layer is used to connect source regions of the first and second driver transistors and the grounding line. The main word line extends in the first direction. The fourth contact pad layer is used to connect the first bit line and the source/drain region of the first transfer transistor. The fifth contact pad layer is used to connect the second bit line and the source/drain region of the second transfer transistor. The sixth contact pad layer is used to connect the source regions of the fi

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