Static RAM memory cell using N-channel MOS transistors

Details Static RAM memory cell using N-channel MOS transistors Static RAM memory cell using N-channel MOS transistors

1991-02-08

1991-09-24

Clawson, Jr., Joseph E.

Static information storage and retrieval

Systems using particular element

Capacitors

365154, 365185, 357 235, 357 51, G11C 11412, G11C 1124

Patent

active

050519514

ABSTRACT:
A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.

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