Static information storage and retrieval – Read/write circuit – Testing
Patent
1988-12-22
1992-07-21
Gossage, Glenn
Static information storage and retrieval
Read/write circuit
Testing
365154, 365226, G11C 2900, G11C 11419
Patent
active
051329298
ABSTRACT:
A static random access memory has a plurality of memory cells. Each memory cell is made up of two high-resistance resistors functioning as load elements, and a flip-flop circuit. The flip-flop circuit is made up of two inverters including MOS transistors which are formed in a substrate and used as drive elements. The sources of the two MOS transistors are coupled to each other and electrically isolated from the substrate. Another MOS transistor is connected between the common source of the flip-flop MOS transistors and the source of a power-supply voltage. A MOS transistor is coupled between the common source of the MOS transistors and the source of a ground voltage. A plurality of bit lines supplies data to, and receives data from, the memory cells. A resistance element is connected between each bit line and the source of the power-supply voltage, and an output terminal outputs the voltage at one end of this resistance element. Two different voltages are applied to the sources of the two MOS transistors. One voltage is applied during normal operation of the memory and the other voltage is applied during leakage current detection testing.
REFERENCES:
patent: 3795859 (1974-03-01), Benante
patent: 4004222 (1977-01-01), Gebhard
patent: 4120047 (1978-10-01), Varadi
patent: 4409679 (1983-10-01), Kurafuji et al.
patent: 4685086 (1987-08-01), Tran
patent: 4760562 (1988-07-01), Ohtani
patent: 4835458 (1989-05-01), Kim
Gossage Glenn
Kabushiki Kaisha Toshiba
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