Static ram cell with trench pull-down transistors and buried-lay

Details Static ram cell with trench pull-down transistors and buried-lay Static ram cell with trench pull-down transistors and buried-lay

1987-07-02

1988-12-27

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, 365189, 357 236, 437 48, G11C 1140, H01L 2170

Patent

active

047945613

ABSTRACT:
Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.

REFERENCES:
patent: 4721987 (1988-01-01), Baglee et al.

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