Static RAM

Static information storage and retrieval – Addressing – Multiple port access

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36518904, G11C 700

Patent

active

052572366

ABSTRACT:
An improved static memory is described which, when used in a dual port cache memory simplifies write cycles by providing latching of decoded address signals which are used in a subsequent memory cycle for writing. Improved logic is described which allows the propagation of data at the rate .function. with timing signals of frequency 1/2.function.. An improved sense amplifier which is isolated from the column lines is the array is used.

REFERENCES:
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patent: 4829471 (1989-05-01), Banerjee et al.
patent: 4870621 (1989-09-01), Nakada
patent: 4933909 (1990-06-01), Cushing et al.
patent: 4954987 (1990-09-01), Auvinen et al.
patent: 4975872 (1990-12-01), Zaiki
patent: 5062081 (1991-10-01), Rudaldue
Functional Simulator for Memory Device, IBM Technical Brochure, vol. 30, No. 5, Oct. 1987.

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