Static power reduction for midpoint-terminated busses

Details Static power reduction for midpoint-terminated busses Static power reduction for midpoint-terminated busses

2011-01-18

2011-01-18

Patel, Nitin C (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S320000, C713S323000

Reexamination Certificate

active

07873843

ABSTRACT:
A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.

REFERENCES:
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patent: 6356106 (2002-03-01), Greeff et al.
patent: 6564331 (2003-05-01), Joshi
patent: 7239565 (2007-07-01), Liu
patent: 7463529 (2008-12-01), Matsubara
patent: 7698581 (2010-04-01), Oh
patent: 2005/0270886 (2005-12-01), Takashima

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