Static memory with low power write port

Details Static memory with low power write port Static memory with low power write port

1998-06-26

1999-12-21

Phan, Trong

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, G11C 1100

Patent

active

060057947

ABSTRACT:
The write port circuits of a static memory cell includes a first conditional conduction path between a first output of the latch and ground active if and only if both a word line input and a write data true bit line input receive active signals. The write port circuit includes a second conditional conduction path between a second output of the latch and ground active if and only if both the word line and a write data complement bit line receive active signals. The first and second conditional conduction paths may be formed by a series connection of the source-drain paths of two transistors. In each conditional conduction path the gate of a first transistor receives a corresponding column signal and the gate of a second transistor is connected to the word line. The first and second transistors for each conduction path may be N-channel MOS transistors formed in a single N-type region. The first and second transistors forming the conditional conduction paths may be in either order. The word line transistors may bee shared between bit line transistors of a single memory cell or of memory cells in plural contiguous adjacent columns. The memory cells may include a plurality of write ports with this inventive write port circuit used for each write port.

REFERENCES:
patent: 4833648 (1989-05-01), Scharrer et al.
patent: 5289432 (1994-02-01), Dhong et al.
patent: 5710742 (1998-01-01), Carter et al.
patent: 5718751 (1998-02-01), Ho et al.
patent: 5742557 (1998-04-01), Gibbins et al.
patent: 5790461 (1998-08-01), Holst

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