Static information storage and retrieval – Read/write circuit – Testing
Patent
1988-11-16
1990-08-21
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Testing
371 211, 371 572, G11C 700, G11C 2900
Patent
active
049512544
ABSTRACT:
Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.
REFERENCES:
patent: 4811299 (1989-03-01), Miyazawa et al.
by Kunnen, legal representative Henricus J.
Davies Thomas J.
O'Connell Cormac
Ontrop Hans
Pfennings, deceased Leonardus C. M. G.
Moffitt James W.
Slobod Jack D.
U.S. Philips Corporation
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