Static memory having self-timing circuit

Details Static memory having self-timing circuit Static memory having self-timing circuit

2002-03-22

2003-11-11

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S154000, C365S233100

Reexamination Certificate

active

06646938

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a static memory having a self-timing circuit for generating timing control signals such as starting signals for a sense amplifier, and more particularly to a static memory which prevents occurrence of a malfunction caused by a leak current of a cell transistor.
2. Description of the Related Art
A static memory has memory cells each of which is a pair of cross-connected inverters. The pair of inverters of the memory cells is connected to a bit line pair via a pair of transfer transistors, and the transfer transistors are conductive according to a driving of a word line, and the inverter pair of the memory cell is connected to the bit line pair, and the inverter pair drives the bit line pair. A voltage difference of the driven bit line pair is detected and amplified by a sense amplifier. Accordingly, a start timing of the sense amplifier is designed so as to come after the voltages of the bit line pair are sufficiently opened.
In a clock synchronous static memory, a timing control signal for starting the sense amplifier is generated after a certain delay time from a supply of a clock, and further in a clock asynchronous static memory, the timing control signal for starting the sense amplifier is generated after a certain delay time from a change of an address.
Preferably, the sense amplifier starting signal is generated at the shortest timing after a predetermined voltage difference is generated between the bit line pair, thereby reducing an access time. However, the bit line drive capability of the memory cells depends on a characteristic of cell transistors, and the characteristic of the cell transistors various due to variances of a manufacturing process. In this manner, as a time for which a predetermined voltage difference is generated between the bit line pair depends on the variances of the process, a sufficient timing margin is provided to generate the sense amplifier starting signal. Even if the timing when the predetermined voltage difference is generated between a bit line pair delays due to the variances towards lower drive capability in the cell transistors, this timing margin allows to prevent a detection of erroneous data by early starting the sense amplifier.
The timing margin of the sense amplifier starting signal prolongs the access time of the memory, and impairs the high-speed performance as the characteristic of the static memory. As a method for solving this problem, a dummy circuit comprising a word line, a memory cell and a bit line is provided, and the sense amplifier starting signal is generated by utilizing a self-timing circuit including this dummy circuit.
FIG. 1
is a configuration diagram of a static memory having a conventional self-timing circuit. In this example, an address Add and a control signal Cont are input in synchronism with a clock CK, and a timing control circuit and a decoder circuit
10
generate timing control signals &phgr;WA, &phgr;SE, a word line selecting signal RS and a column selecting signal CS. A word line driver
12
drives a word line WL according to the word line selecting signal RS generated by the decoder circuit to select a memory cell MC within a memory cell array MCA. The selected memory cell MC drives a bit line pair BL, XBL, and a voltage of the bit line pair selected by a column switch
14
is amplified by a sense amplifier
18
. A data output Dout is output from an output circuit
22
. The above is a readout operation. In a write operation, a data input Din is input into an input circuit
20
, and the selected memory cell MC is driven by a write amplifier
16
, so that data is written.
In the readout operation, a timing of a starting signal &phgr;SA for starting the sense amplifier
18
is controlled by the self-timing circuit comprising a dummy word line DWL, a self-timing dummy memory cell SDMC, a dummy bit line pair DBL, XDBL and a dummy timing control circuit
24
.
The dummy word line DWL having a plurality of load dummy cells LDMC, a self-timing dummy memory cell SDMC and a dummy bit line pair DBL, XDBL having the plurality of load dummy cells LDMC are provided with a configuration equivalent to a normal memory cell array.
FIG. 2
is a timing chart diagram of a readout operation of FIG.
1
. In the readout operation, in a status that the bit line pair BL, XBL is pre-charged at H level, the word line driver
12
drives the selected word line WL as well as the dummy word line DWL. A self-timing dummy memory cell SDMC is selected in response thereto to drive the dummy bit line pair DBL, XDBL. Specifically, a potential level of one dummy bit line is decreased from the pre-charge level. A change &Dgr;V of the voltage of this dummy bit line pair is detected, and a dummy timing control circuit
24
generates a self-timing signal &phgr;SLF. The timing control circuit
10
generates the sense amplifier starting signal &phgr;SA in response to this self-timing signal &phgr;SLF.
On the other hand, the memory cell MC selected by driving of the selected word line WL drives the bit line pair BL, XBL. In response to the sense amplifier starting signal &phgr;SA, the sense amplifier
18
detects the voltage difference &Dgr;V of the selected bit line pair to drive one of the bit line pair down to sufficiently low level.
According to the dummy circuit, drive capability of the memory cell MC in the memory array varies due to process variances, but drive capability of the dummy memory cell SDMC similarly varies. Accordingly, a timing when a voltage difference to be detected by the sense amplifier occurs in the bit line pair BL, XBL driven by the memory cell MC and a timing when a predetermined voltage difference occurs in the dummy bit line pair DBL, XDBL driven by the dummy memory cell SDMC vary in the same direction according to the process variances. As a result, the sense amplifier starting signal &phgr;SA is always generated at an optimal timing.
Incidentally, in
FIG. 2
, a reduction in a voltage of the dummy bit line pair DBL, XDBL is faster than a normal bit line pair BL, XBL. This is because the self-timing dummy memory cell SDMC is configured by connecting a plurality of memory cells in parallel, so as to have a higher drive capability than a piece of memory cell. Thus, a voltage change of the dummy line pair is made faster than the normal bit line pair, thereby making it possible to generate a self-timing signal &phgr;SLF at an early timing.
FIG. 3
is a detailed circuit diagram of the dummy bit line pair and the dummy memory cell connected thereto in the prior art. The self-timing dummy memory cell SDMC has a latch circuit in which a pair of inverters INV
1
,
2
are cross-connected to each other, and transfer transistors N
5
, N
6
for connecting then to the bit line pair DBL, XDBL. A plurality of the dummy memory cells SDMC (not shown) are connected in parallel to the dummy word line DWL. Furthermore, load dummy memory cells LDMC
1
,
2
also have the pair of inverters INV
1
,
2
and the transfer transistors N
5
, N
6
, similarly. However, word lines LDWL
1
,
2
connected thereto are fixed to a ground potential Vss. Accordingly, the load dummy memory cells are provided only for giving the same parasitic capacitance as the normal memory cell to the dummy bit line pair DBL, XDBL, and does not drive the dummy bit line pair.
As the plurality of self-timing dummy memory cells SDMC are provided in parallel, one of a pair of nodes n
1
, n
2
of an inverter pair is fixed to a potential at H level or L level so that a conflict does not generate in operations of driving the dummy bit line pair when the dummy word line DWL is driven. In an example of
FIG. 3
, the node n
1
is connected to a power supply Vcc. As a result, according to the driving of the dummy word line DWL, a right-side dummy bit line XDBL among the dummy bit line pair which has been pre-charged in advance is driven to L level side by the inverter INV
1
via the transfer transistor N
6
. In other words, the dummy bit line XDBL is driven according to an illustrat

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