Static memory cell with load circuit using a tunnel diode

Details Static memory cell with load circuit using a tunnel diode Static memory cell with load circuit using a tunnel diode

1997-12-17

2000-08-15

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Flip-flop

365188, 365104, 365 72, 365115, 365175, G11C 1134

Patent

active

061046310

ABSTRACT:
A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (V.sub.f) of the tunnel diode (32) controls the V.sub.gs transfer curve (56) of the load transistor.

REFERENCES:
patent: 4901279 (1990-02-01), Plass
patent: 5487037 (1996-01-01), Lee
patent: 5526304 (1996-06-01), Kawamura
patent: 5724292 (1998-03-01), Wada
patent: 5745407 (1998-04-01), Levy et al.
patent: 5751630 (1998-05-01), Roberts
patent: 5757696 (1998-05-01), Matsuo et al.
patent: 5771190 (1998-06-01), Okamura
patent: 5986923 (1996-11-01), Zhang et al.

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