Static memory cell

Details Static memory cell Static memory cell

2000-08-15

2001-11-20

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Diffusing a dopant

C438S323000, C438S238000

Reexamination Certificate

active

06319800

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to a memory device having static memory cells fabricated with a single bit line.
BACKGROUND OF THE INVENTION
Static random access memories (SRAM's) comprise static memory cells which are designed to operate as a data latch. The memory cells typically use access transistors to couple the memory cell to a pair of complementary bit lines. The memory cell access transistors are selectively activated using a word line signal. Sense amplifier circuitry is used to detect voltage differentials between the bit lines. A pair of cross coupled pulldown transistors are typically connected to the access transistors and are used to latch data.
Different static memory cell integrated circuit layouts have been used, however, these cells either have asymmetrical current paths through the pulldown transistors or require two word lines. The asymmetrical memory cells tend to be both unstable and susceptible to process variables such as two dimensional encroachment. Memory cells which use two word lines are more electrically symmetrical, but require additional die area for the second word line.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory cell which has the stability of the dual word line memory cell while requiring die area similar to the single word line memory cell.
SUMMARY OF THE INVENTION
The above mentioned problems with static memory cells and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A static memory cell is described which has a single word line and uninterrupted active area.
In particular, the present invention describes a static memory cell comprising access transistors coupled to bit lines, each of the access transistors having a gate connected to a single word line, and pulldown transistors connected to the access transistors. Each of the pulldown transistors has a gate fabricated essentially parallel to the single word line in a plan view.
In an alternate embodiment, an SRAM cell is described which comprises a first access transistor having a drain connected to a first bit line and a gate connected to a single word line. The cell includes a first pulldown transistor having a drain connected to a source of the first access transistor, a source coupled to a bias voltage, and a gate fabricated parallel to the single word line in a plan view. A second access transistor is provided which has a drain connected to a second bit line and a gate connected to the single word line. Finally, a second pulldown transistor is provided which has a drain connected to a source of the second access transistor, a source coupled to the bias voltage, and a gate fabricated parallel to the single word line in a plan view.
In another embodiment, a static random access memory device is described which comprises an array of static memory cells. the static memory cells comprise a first access transistor connected to a first pulldown transistor thereby defining a first current path, and a second access transistor connected to a second pulldown transistor thereby defining a second current path substantially equal to the first current path. The memory has a plurality of data communication paths for bi-directional data communication with an external processor, and an address decoder for decoding an address signal provided by the external processor and accessing the array.
In yet another embodiment, an SRAM cell is provided which comprises a first access transistor fabricated in a first silicon active area having a drain connected to a first bit line, and a gate connected to a single word line. A first pulldown transistor is fabricated in the first silicon active area having a drain connected to a source of the first access transistor, and a source coupled to a bias voltage thereby defining a first electrical current path through the first silicon active area. A second access transistor fabricated in a second silicon active area having a drain connected to a second bit line, and a gate connected to the single word line. A second pulldown transistor fabricated in the second silicon active area having a drain connected to a source of the second access transistor, and a source coupled to the bias voltage thereby defining a second electrical path through the second silicon active area which is substantially symmetrical with first electrical current path.


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