Static memory cell

Details Static memory cell Static memory cell

1990-03-09

1991-08-13

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365190, 365156, G11C 1134, G11C 700

Patent

active

050401467

ABSTRACT:
Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.

REFERENCES:
patent: 4768172 (1988-08-01), Sasaki
patent: 4792924 (1988-12-01), Rubinstein
Weiss, H. et al., "Integrierte MOS Schaltungen", Springer-Verlag Berlin, Heidelberg, 1982, pp. 244-245.

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