Static memory adopting layout that enables minimization of cell

Details Static memory adopting layout that enables minimization of cell Static memory adopting layout that enables minimization of cell

1998-12-03

2000-06-27

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

365174, G11C 1100

Patent

active

060814446

ABSTRACT:
A static memory in which memory cells each have the components thereof laid out so that the area of each memory cell can be further reduced in compliance with improvement in technology of separating devices. The static memory includes CMOS memory cells each having two cross-coupled inverters, in each of which an n-channel transistor and p-channel transistor are connected in series with each other. At least one of the contacts used to cross-couple the two inverters is located in a region other than a region enclosed by the diffused sources and drains of the n-channel transistors and p-channel transistors included in the memory cell.

REFERENCES:
patent: 5247198 (1993-09-01), Homma et al.
patent: 5818080 (1998-10-01), Kuriyama

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