Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-05-01
2001-05-01
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S030000
Reexamination Certificate
active
06225654
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer memories and more particularly, to computer memories based on ferroelectric thin films.
Background of the Invention
Computer memories may be conveniently classified in terms of whether or not the memory retains the information stored therein when power is removed from the memory. Conventional DRAMs and SRAMs are examples of memories that lose their contents when power is removed. EEPROM and flash RAM are examples of non-volatile memories. The cost of non-volatile memories per bit remains sufficiently high to discourage their use in many applications. In addition, the underlying memory structures may only be written a relatively small number of times compared to volatile memories. For example, an EEPROM memory cell can only be written approximately 10
4
times. In addition, the time required to write data into an EEPROM is many longer than that required to write volatile memories. Hence, the use of EEPROM cells is limited to a relatively limited class of applications.
One class of non-volatile memory that holds the potential for providing increased write cycles and faster writes is based on the ferroelectric thin films. These memories may be divided into two types, those based on capacitors having ferroelectric dielectrics and those based on a structure analogous to a FET in which the gate oxide is replaced by a ferroelectric. The capacitor-like memories are based on a capacitor having a ferroelectric dielectric which may be polarized in one of two directions. The direction of polarization is used to store information, a “1” corresponding to one direction of polarization and a “0” corresponding to the other direction of polarization. The polarization of the dielectric is maintained when power is removed from the system, thus providing non-volatile operation. The memory is read by applying a potential in a direction that polarizes the memory in one of the two states and then detecting any current that flows during this programming cycle. A current flow is indicative of the capacitor having been in the opposite polarization state prior to the read pulse. In this case, the memory must be re-written after the read, since the read pulse will have changed the state of the capacitor. Hence, this type of memory cell is often referred to as a destructively read-out memory cell (DRO). While DRO memories may be written many more times than conventional EEPROM memories, commercial realizations of this type of memory have been limited by a number of factors including imprint and speed.
Memory cells based on the analog of the conventional field effect transistor hold the promise of avoiding the limitations of the DRO type devices. This type of memory may be viewed as a ferroelectric capacitor in which the top plate is replaced by a semiconducting material having two electrodes affixed thereto. The conductivity of the semiconducting layer depends on the direction of polarization of the ferroelectric dielectric layer. In one direction of polarization, the remanent field depletes the semiconducting layer of carriers leading to a high resistivity state for the layer. In the other direction of polarization, the semiconductor layer is in a low resistivity state. By placing a small potential difference across the electrodes on the semiconducting layer, the resistivity of the layer may be measured. Since this read operation does not change the polarization of the dielectric layer, these devices are referred to as nondestructively read-out memories (NDRO memories). Since the state of the dielectric does not change during read, these memories can be read faster and require lower power than the DRO memories. These memories also avoid the imprint problems that have blocked the commercialization of DRO memories.
The NDRO devices, however, have a lower information retention time than EEPROM's which typically retain their information for a period of 10 years. The prior art NDRO devices, in contrast, have been limited to a retention time of the order of 1 year.
Broadly, it is the object of the present invention to provide an improved NDRO memory device based on a ferroelectric FET.
It is a further object of the present invention to provide a ferroelectric FET memory cell that retains its information significantly longer than prior art ferroelectric FET memory cells.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is an improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO
3
wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.
REFERENCES:
patent: 5116643 (1992-05-01), Miller et al.
patent: 5198269 (1993-03-01), Swartz et al.
patent: 5578846 (1996-11-01), Evans, Jr. et al.
patent: 0046680 (1983-03-01), None
Evans, Jr. Joseph T.
Tuttle Bruce A.
Warren William L.
Abraham Fetsum
Radiant Technologies, Inc
Ward Calvin B.
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