Static-dynamic logic circuit

Details Static-dynamic logic circuit Static-dynamic logic circuit

1996-09-30

1998-12-22

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 21, 326121, H03K 19096, H03K 190948

Patent

active

058523731

ABSTRACT:
A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.

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