Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-03-14
2009-02-17
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S005000, C711S103000, C711S127000, C714S701000, C714S756000, C714S762000, C714S764000, C365S185010, C365S185030
Reexamination Certificate
active
07493457
ABSTRACT:
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┌N/M┐ cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.
REFERENCES:
patent: 2632058 (1953-03-01), Gray
patent: 5434825 (1995-07-01), Harari
patent: 6046935 (2000-04-01), Takeuchi
patent: 6088261 (2000-07-01), Nakajima
patent: 6522580 (2003-02-01), Chen
patent: 6631491 (2003-10-01), Shibutani et al.
patent: 6643188 (2003-11-01), Tanaka
patent: 6684289 (2004-01-01), Gonzalez et al.
patent: 6707713 (2004-03-01), Parker et al.
patent: 6772383 (2004-08-01), Quach et al.
U.S. Appl. No. 11/061,634 Lasser : States Encoding In Multi-Bit Flash Cells For Optimizing Error Rate filed Feb. 22, 2005.
Friedman Mark M.
Patel Kaushikkumar
SanDisk IL. Ltd
Sough Hyung
LandOfFree
States encoding in multi-bit flash cells for optimizing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with States encoding in multi-bit flash cells for optimizing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and States encoding in multi-bit flash cells for optimizing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4061445