States encoding in multi-bit flash cells for optimizing...

Details States encoding in multi-bit flash cells for optimizing... States encoding in multi-bit flash cells for optimizing...

2011-08-30

2011-08-30

Patel, Kaushikkumar (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S103000, C714S756000, C714S773000, C365S185030

Reexamination Certificate

active

08010755

ABSTRACT:
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.

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