State retention for formal verification

Details State retention for formal verification State retention for formal verification

2007-06-30

2010-06-29

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07747971

ABSTRACT:
Verification model of static state retention behavior of a state saving element design during power shut off of the state saving element in an integrated circuit design including: creating in a computer readable medium a model of a single edge triggered state saving element; and creating in the computer readable medium clock gate logic that suspends saving of new states by the single state saving element upon the occurrence of a first state retention signal in preparation for power shut off.

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patent: 2007/0271536 (2007-11-01), Seawright et al.
patent: 2009/0144684 (2009-06-01), Seawright et al.

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