Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-29
2002-10-22
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06470481
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to design verification systems. More particularly, the present invention relates to management of co-verification of a target design.
BACKGROUND OF THE INVENTION
Designers of complex electronic systems often use verification tools to simulate, analyze and/or verify component designs. Various technologies exist to assist the designer in this process. One co-verification scheme allows two components of a system design (e.g., hardware and software) to be simulated simultaneously and to interact with each other such that a complete system can be verified. This is referred to as “co-simulation.” Other co-verification schemes include software simulation/hardware emulation.
One drawback to hardware/software co-simulation is that the typical speed at which hardware simulation can be performed is much slower that the typical speed at which software simulation can be performed. Thus, hardware simulation limits the speed of co-simulation. Relatively slow hardware simulation results in co-simulation systems that cannot provide complete design co-verification for complex designs including both hardware and software.
One solution to the limitations imposed by relatively slow hardware simulation is to “de-couple” time synchronization of hardware and software simulation in order to accelerate software simulation for selected portions of the target design verification process. The software simulation component is allowed to operate at full speed without waiting for signals to be received from the hardware simulation component. During this acceleration, the hardware simulation component is either suspended or performs simulation independent of the software simulation.
One disadvantage of this acceleration scheme is that verification details are lost because intermediate results are not communicated between the software and hardware verification components. If a hardware design includes certain hardware elements, such as timers and/or counters, that are used to trigger software events, such as interrupts, accurate co-simulation cannot be achieved if portions of the co-simulation are accelerated. Thus, in order to accomplish accurate co-simulation of a target design, full co-simulation may be required, which can be a very time consuming process.
What is needed is a method and apparatus that allows co-verification acceleration without loss of timing information.
SUMMARY OF THE INVENTION
A method and apparatus for state management in a co-verification system is described. A transition from a synchronized co-verification mode to an accelerated coverification mode is detected. In response to the transition, a first portion and a second portion of a target design are verified independently. An architectural state corresponding to the second portion is maintained based on verification of the first portion, wherein the architectural state is maintained as part of verification of the first portion. Eventually, co-verification transitions back to synchronized co-verification mode in response to a predetermined architectural state.
REFERENCES:
patent: 5960182 (1999-09-01), Matsuoka
patent: 5987243 (1999-11-01), Aihara
patent: 6052524 (2000-04-01), Pauna
patent: 6212489 (2001-03-01), Klein
Brouhard Michael C.
Wilson John
Blakely , Sokoloff, Taylor & Zafman LLP
Niebling John F.
Whitmore Stacy
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