State machine with a dynamic clock gating function

Details State machine with a dynamic clock gating function State machine with a dynamic clock gating function

1998-11-05

2001-03-13

Lee, Thomas (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S600000

Reexamination Certificate

active

06202166

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87112423, filed Jul. 29, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a state machine, and in particular to a state machine with a dynamic clock gating function, leading to a low power consumption.
2. Description of the Related Art
As shown in
FIG. 1
a
, a traditional state machine includes a next state logic
10
and a current state logic
12
. The current state logic
12
consists of a plurality of flip-flops. A clock signal is directly inputted to the clock input terminal of each flip-flop. Thus, the total power consumption caused by a state transition of the clock signal is estimated by the following formula:
&Sgr;½C
Li
V
2
ƒ
i
where the C
Li
is a total capacitance of all capacitors which are charged/discharged in the current state logic
12
following the state transition of the clock signal with a frequency of f
i
.
As an example, a traditional resettable D-type flip-flop is shown in FIG.
2
.
In
FIG. 2
, an inverter
20
receives an external clock signal CK and then transmits a transfer control signal CKB. The transfer control signal CKB is reverted into a complementary transfer control signal {overscore (CKB)} by an inverter
22
, wherein the transfer control signal CKB and the complementary transfer control signal {overscore (CKB)} are used to control the on/off states of a CMOS transmission gate.
When the external clock signal CK is at a low logic level, the transfer control signal CKB is at a high logic level and the complementary transfer control signal {overscore (CKB)} is at a low logic level. At this point, transmission gates
24
and
26
are closed while transmission gates
28
and
30
are open. On the other hand, when the external clock CK is at a high logic level, the transfer control signal CKB is at a low logic level and the complementary transfer control signal {overscore (CKB)} is at a high logic level. At this time, the transmission gates
24
and
26
are open while the transmission gates
28
and
30
are closed. In line with the state transition of the clock signal between the high and low logic levels, capacitors, including the input and output capacitor of the inverters
20
and
22
and the input capacitors of the transmission gates
24
,
26
,
28
and
30
, are charged/discharged, causing a power consumption. No matter at which state the state machine is, the power consumption remains constant even if the state machine is at an idle state. This causes a problem of an excess power consumption.
SUMMARY OF THE INVENTION
In view of the above, an object of the invention is to provide a state machine with a dynamic clock gating function for resolving the problem of an excess power consumption as stated in the prior art.
To attain the above-mentioned object, the state machine with a dynamic clock gating function according to the invention at least includes a next state logic, a plurality of flip-flops, a plurality of OR gates and a gating clock control logic. The next state logic is used to output a next state. The data input terminal of each flip-flop is electrically coupled to the output terminal of the next state logic while the data output terminal of each flip-flop is electrically coupled to the input terminal of the next state logic. The flip-flops are combined to obtain a current state. A first input terminal of each OR gate receives an external clock signal while the output terminal of each OR gate is electrically coupled to the clock input terminal of a corresponding flip-flop. The input terminal of the gating clock control logic is electrically coupled to the data output terminal of each flip-flop while the output terminal of the gating clock control logic is electrically coupled to a second input terminal of each OR gate. The gating clock control logic judges whether to gating the clock signal of each flip-flop based on the current state.
Accordingly, in the state machine with a dynamic clock gating function according to the invention, the gate clock control logic is used to gate a clock signal input to flip-flops which do not require a clock sample input. Thus, the capacitance of capacitors which are charged/discharged following the state transition of the clock signal is greatly reduced, thereby decreasing excess power consumption.


REFERENCES:
patent: 5461649 (1995-10-01), Bailey et al.
patent: 5463655 (1995-10-01), Llewellyn
patent: 5949266 (1999-09-01), Hinds et al.
patent: 5974555 (1999-10-01), Nakayama
patent: 5994935 (1999-11-01), Ueda et al.

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