State machine design for generating half-full and half-empty fla

Details State machine design for generating half-full and half-empty fla State machine design for generating half-full and half-empty fla

1995-12-06

1998-09-15

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711156, G06F 1200

Patent

active

058093397

ABSTRACT:
A state machine design which can be used to realize extremely short flag generation delays, also realizing the benefit of having an extremely high MTBF. A set of next state variables are generated from a combination of three previous state variables and three additional inputs representing a logical "OR" of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.

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