Standby leakage current reduction circuit and semiconductor...

Details Standby leakage current reduction circuit and semiconductor... Standby leakage current reduction circuit and semiconductor...

2008-07-08

2008-07-08

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C365S229000

Reexamination Certificate

active

07397721

ABSTRACT:
Embodiments of the invention provide a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit. The invention provides a circuit adapted to reduce standby leakage current in a semiconductor memory device comprising memory cells. The circuit comprises a bias signal generator adapted to generate a bias signal, wherein a voltage level of the bias signal is set in accordance with a result of a standby leakage current test. The circuit further comprises a ground voltage controller adapted to receive the bias signal from the bias signal generator and to control a level of a voltage apparent on a virtual ground terminal in response to the bias signal while the semiconductor memory device is in a standby mode.

REFERENCES:
patent: 6525983 (2003-02-01), Wilkins
patent: 6611451 (2003-08-01), Houston
patent: 6836179 (2004-12-01), Mizuno et al.
patent: 6977519 (2005-12-01), Bhavnagarwala et al.
patent: 7145383 (2006-12-01), Mizuno et al.
patent: 7164616 (2007-01-01), Miller et al.
patent: 7271615 (2007-09-01), Afghahi et al.
patent: 2007/0040575 (2007-02-01), Afghahi et al.

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