Standard cell, standard cell library, semiconductor device,...

Details Standard cell, standard cell library, semiconductor device,... Standard cell, standard cell library, semiconductor device,...

2007-11-27

2007-11-27

Pert, Evan (Department: 2826)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C257S206000, C257S499000, C257SE27001

Reexamination Certificate

active

11300304

ABSTRACT:
Of a plurality of standard cells in which an N-well region and a P-well region are vertically formed, some standard cells have a border line between the N-well region and the P-well region which is set to be a low height (first height), and other standard cells have a border line between the N-well region and the P-well region which is set to be a high height (second height), depending on the size of a transistor formed in the standard cell. Although these standard cells have different border lines, a standard cell for linking the border lines is provided. In such a standard cell, an empty space is created by forming a small-size transistor therein, and the empty space is utilized so that, for example, a left end of the border line is set to have the first height and a right end of the border line is set to have the second height, whereby the border line is converted so as to link the heights therein.

REFERENCES:
patent: 6849906 (2005-02-01), Maeno et al.
patent: 2004-079702 (2004-03-01), None
Lee, Bu-Yeol., et al. “Low-Power CMOS Standard Cell Library.” (w/Partial English translation) URL: http:/
e.nikkeibp.co.jp/IPJapan/ipaward/990618ipa8.html.

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