Standard cell, standard cell array, and system and method...

Details Standard cell, standard cell array, and system and method... Standard cell, standard cell array, and system and method...

2000-06-27

2004-08-31

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06785877

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a standard cell formed on a semiconductor substrate, a standard cell array formed on a semiconductor substrate, and a system and a method for placing and routing standard cells.
As a layout design technology for realizing a LSI (large scale integrated circuit) on a semiconductor substrate with a high integration density for a short period of time, a standard cell type LSI design technology is widely utilized, in which small unitary circuits such as an inverter and an NAND gate are previously prepared as standard cells, and those standard cells are placed in the form of an array and interconnected to form an LSI.
Referring to
FIG. 18A
, a layout diagram of a standard cell type LSI is illustrated. A plurality of cell arrays are placed, each of the cell arrays being formed of a plurality of function cells
106
having the same width (height in the drawing) and placed in the form of an array. A routing channel
1801
is reserved between each pair of adjacent cell arrays. In the routing channel
1801
, there are located an inter-cell connection
1802
for interconnecting between cells included in the same cell array, and an inter-array connection
1803
for interconnecting between cells which are included in different cell arrays, respectively.
Referring to
FIG. 18B
, there is shown a pattern diagram of the inside of one typical prior art standard cell. The shown standard cell is a function cell
106
a
having an inverter function. In
FIG. 18B
, the reference number
111
designates an N-well, and the reference number
112
indicates a P-type diffused layer. The reference number
113
shows an N-type diffused layer, and the reference number
114
denotes a polysilicon. The reference number
115
designates a contact hole between the P-type or N-type diffused layer and a first level metal. The reference number
116
indicates a contact hole between the polysilicon and the first level metal. The reference number
117
shows the first level metal. The reference number
120
denotes a VDD power supply line formed of the first level metal. The reference number
121
designates a VSS power supply line formed of the first level metal. In the N-well
111
, a P-channel MOS transistor having a source and a drain formed of the P-type diffused layer
112
is formed. In a P-type substrate region at the outside of the N-well, an N-channel MOS transistor having a source and a drain formed of the N-type diffused layer
113
is formed.
In the prior art standard cell, all the cells have the same constant width (height in FIG.
18
B), and the VDD power supply line
120
and the VSS power supply line
121
having the same fixed width are located at an upper end portion and at a lower end portion of the cell, respectively, as shown in FIG.
18
B. An area between the pair of power supply lines in the cell is used to form the transistors included in the cell and to locate interconnections between terminals (contacts) within the cell (called an “in-cell wiring” in this specification). On the other hand, the routing channel has to be used for the interconnection between cells. However, the width of the cell is determined to meet a function cell such as a flipflop which needs a number of transistors and a complicated in-cell wiring. Therefore, the following problem has been encountered in the prior art standard cell. In a relatively simple function cell such as an inverter and a 2-input NAND gate which has a simple in-cell wiring, although there arise many empty areas for the first level metal, the empty areas could not be utilized for the inter-cell connection. In addition, the power supply lines extending through all the standard cells have the constant width, and it is not so easy to change the width of the power supply lines in accordance with the magnitude of a required power supply current.
Under this situation, Japanese Patent Application Pre-examination Publication No. JP-A-06-169016 discloses a standard cell having an empty area which is provided between a power supply line and an in-cell wiring area and which can be utilized for the inter-cell connection. Referring to
FIG. 19A
, there is shown a wiring area diagram of a standard cell in accordance with this second prior art. An empty area
123
is provided between the VDD line
120
of the first level metal and an in-cell wiring area
122
, and another empty area
124
is provided between the VSS line
121
of the first level metal and the in-cell wiring area
122
. These empty areas
123
and
124
can be utilized for the inter-cell connection so as to realize an elevated integration density.
In addition, Japanese Patent Application Pre-examination Publication No. JP-A-03-062551 discloses a standard cell having a device formation area extending into an outside of the power supply line. Referring to
FIG. 19B
, there is shown a wiring area diagram of a standard cell in accordance with this third prior art. An in-cell wiring area
122
is provided between the VDD line
120
and the VSS line
121
, similarly to the first prior art example shown in FIG.
18
B. However, a device formation area
125
depicted by a chain line extends into an outside of each power supply line. Since this outside area can be utilized as a wiring area, the outside area can be utilized for the inter-cell connection. In addition, even if the position of the power supply lines is standardized for all the cells, it is possible to freely set a substantial cell width determined by the size of the device formation area.
Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-05-055381 proposes a standard cell having no power supply line pattern. Referring to
FIG. 19C
, there is shown a wiring area diagram of a standard cell in accordance with this fourth prior art. The standard cell includes only an in-cell wiring area
122
including transistors formed in the cell and a wiring pattern for connecting between terminals in the cell. After a required number of standard cells are placed in the form of an array, a power supply line pattern which has a line width determined on the basis of the length of the cell array and a power consumption, is generated to connect to each standard cells. Therefore, the power supply line can have an optimum line width.
However, the standard cell of the second prior art are difficult to optimize the width of the power supply line, and are restricted to have a constant cell width. The standard cell of the third prior art is difficult to optimize the width of the power supply line. The standard cell of the fourth prior art are restricted to have a constant cell width. In addition, since the device formation area is not used for the inter-cell connection, the wiring density is low.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a standard cell, a standard cell array, and a system and a method for placing and routing standard cells, which have overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a standard cell, a standard cell array, and a system and a method for placing and routing standard cells, capable of forming an inter-cell connection in an area between a power supply line and an in-cell wiring area and also capable of ensuring the power supply line having an optimum line width, without a restriction requiring a constant cell width.
According to a first aspect of the present invention, there is provided a standard cell comprising a power supply terminal of a diffused layer, an input terminal of a first level metal and an output terminal of the first level metal.
More specifically, the standard cell in accordance with the present invention comprises a function circuit including at least one P-channel transistor and at least one N-channel transistor; a first power supply terminal for supplying a first power supply voltage to the at least one P-channel transistor, a second power supply terminal for supplying a second power supply voltage to the at least one N-

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