Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-10-24
2001-01-09
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, 72, 72, C726S006000, C726S006000, C726S006000
Reexamination Certificate
active
06173436
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to reset circuits and particularly to reset circuits used when ramping up the power supply voltage of a integrated circuit device.
2. State of the Art
In digital integrated circuits (ICs) it is often desirable, upon powering up, to reset portions of the IC so that given logic within the circuit is in a known state. However, when powering up an integrated circuit, the power supply voltage is often ramped up to the intended full level of the power supply voltage instead of directly applying full power. During this time, the integrated circuit is in an intermediate state and any reset signal generated while the circuit is being powered up may appear to be at a digital level other than the intended reset digital level. Consequently, the reset signal is generally provided to the remainder of the integrated circuit a short delay time after the power supply voltage has been applied to the power supply ports.
In general, reset circuitry (referred to as power-on reset (POR) circuitry) detects the power supply voltage as its being ramped to full power and delays the application of the reset signal for a given amount of time after the power supply has been applied. Currently, PORs are implemented as a RC circuit made up of resistive and capacitive elements. The power supply voltage is coupled to the input of the POR and the output of the POR is a delayed power supply signal which functions to reset the IC.
The physical appearance of the IC layout of the standard analog POR is easily identifiable within the integrated circuit chip. Specifically, when viewing an integrated digital circuit with a microscope, it is possible to identify the capacitive and resistive layout elements that make up the POR. In addition, the POR clearly appears as an analog circuit when compared to the remaining digital circuitry making up the IC. The disadvantage of being able to visually identify where the POR is located on the IC is that it provides a manner in which to determine other architectural aspects of the IC and potentially provides a manner in which to access the IC in a way not intended by the manufacturer. It is well known in the integrated circuit industry that reverse engineering has become a prevalent concern for IC designers and manufacturers and identifying the POR location is one means in which reverse engineering can be facilitated. Furthermore, knowing the location of the POR on a digital circuit can also provide a way in which to access or alter information stored within the integrated circuit thus presenting a potential security problem.
The present invention is a method of designing a POR to make it difficult or impossible to visually detect and locate within an integrated circuit layout.
SUMMARY OF THE INVENTION
A method of implementing a POR entirely out of digital elements so as to make it difficult to visually detect within an digital integrated circuit (IC) layout design is described.
In one embodiment of the present invention, each functional block of the POR is implemented using standard layout cells and devices used to design the remainder of the IC that the POR resides in.
In another embodiment of the present invention a digital circuit integrated layout has a first portion corresponding to a digitally designed POR circuit implemented using standardized layout cells and routing and a second portion corresponding to the remainder of the integrated circuit also implemented using standardized layouts cells and routing such that the POR circuit is visually non-discernible within the integrated circuit layout.
In another embodiment of the present invention, certain devices in the POR circuit are implemented so that they visually appear in the layout as these devices would in a digital circuit. For instance, in one embodiment, transistors within the digitally implemented POR that need to be designed with gate widths greater than the standard digital transistor gate width due to the PORs intrinsic analog nature are designed instead using two standard width transistors so as to give the appearance of a digital circuit instead an analog circuit.
In one embodiment of the digitally designed POR of the present invention the circuit includes a level detector for indicating when the power supply reaches a predetermined voltage level, an oscillation signal generator which is enabled when the power supply reaches the predetermined level and which, once enabled, generates a digital oscillation signal, and a control circuit for outputting the power-on-reset signal after a predetermined number of cycles of the oscillation signal.
In another embodiment of the digitally designed POR of the present invention the circuit includes a voltage level detector as described above, set/reset latching circuitry, an oscillator, and counting circuitry. The set/reset latching circuitry has its set input coupled to the output of the level detector and its rest input coupled to a STOP control signal. The oscillator, which is enabled by the latching circuitry when the power supply reaches the predetermined level, generates a digital oscillation signal. The digital oscillation signal is coupled to the counting circuitry which, after a predetermined number of cycles corresponding to a desired delay time, outputs the STOP control signal. Once the STOP control signal is provided to the reset input of the latching circuitry, the latching circuitry disables the oscillation signal generator and also outputs the power-on-reset signal to the remainder of the integrated circuit. The amount of delay that is desired can be varied by modifying the counting circuitry to count more or less cycles.
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Ciccone John C.
Yup Bing L.
Burns Doane Swecker & Mathis L.L.P.
Lintz Paul R.
Siek Vuthe
VLSI Technology Inc.
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