Standard cell integrated circuit layout definition having functi

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

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716 18, 716 8, G06F 1750

Patent

active

060932147

ABSTRACT:
A method of forming a layout definition of a semiconductor integrated circuit includes generating a netlist of functionally committed standard cell instances and the electrical interconnections between the standard cell instances. The standard cell instances are then placed in a layout pattern. Also, functionally uncommitted base cells are place with the standard cell instances in the layout pattern. The base cell instances may be metalized, if needed, in later processing steps to implement design changes by adding additional logical functions.

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