Stacked type chip package structure including a chip package...

Details Stacked type chip package structure including a chip package... Stacked type chip package structure including a chip package...

2009-04-22

2010-11-16

Monbleau, Davienne (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified encapsulant

C257S686000, C257S777000, C257S676000, C257SE25006

Reexamination Certificate

active

07834469

ABSTRACT:
A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip.

REFERENCES:
patent: 6995459 (2006-02-01), Lee et al.
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patent: 2005/0023667 (2005-02-01), Lin et al.
patent: 2007/0164403 (2007-07-01), Huang et al.
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patent: 2005317998 (2005-11-01), None
Chinese First Examination Report of China Application No. 20081009856710, dated Jun. 5, 2005.

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