Stacked type chip package structure

Details Stacked type chip package structure Stacked type chip package structure

2011-06-21

2011-06-21

Pizarro, Marcos D. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S687000, C257SE25006

Reexamination Certificate

active

07964953

ABSTRACT:
A stacked type chip package structure including a backplate, a circuit substrate, a first chip, a second chip, and a conductive film is provided. The backplate comprises a circuit layer. The circuit substrate is disposed on the backplate, and has an upper surface and an opposite lower surface. Besides, the circuit substrate has a receiving hole corresponding to the backplate. The first chip is disposed inside the receiving hole, and the first chip is electrically connected to the circuit substrate through the circuit layer of the backplate. The second chip is disposed above the first chip, and is electrically connected to the circuit substrate. The conductive film is disposed between the first chip and the second chip, wherein the conductive film is electrically connected to a ground of the circuit substrate.

REFERENCES:
patent: 2002/0079568 (2002-06-01), Degani et al.
patent: 2006/0175696 (2006-08-01), Kim

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